S. Kanakasabapathy

发表

Demonstration of highly scaled FinFET SRAM cells with high-κ/metal gate and investigation of characteristic variability for the 32 nm node and beyond

W. Haensch, Y. Zhang, L. Chang, 2008, 2008 IEEE International Electron Devices Meeting.

Systematic studies on reactive ion etch-induced deformations of organic underlayers

Yayi Wei, Markus Brink, Sebastian Engelmann, 2011, Advanced Lithography.

A statistical study of magnetic tunnel junctions for high-density spin torque transfer-MRAM (STT-MRAM)

S. Le, S. Kanakasabapathy, J. Nowak, 2008, 2008 IEEE International Electron Devices Meeting.

Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications

L. H. Vanamurth, D. Yang, T. Adam, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08µm2 SRAM cell

T. Adam, T. Standaert, M. Khare, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond

H. Sunamura, T. Yamamoto, B. Haran, 2010, 2010 Symposium on VLSI Technology.

Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drain

T. Adam, J. Holt, B. Haran, 2006, 2009 Symposium on VLSI Technology.

Assessment of fully-depleted planar CMOS for low power complex circuit operation

K. Tabakman, S. Wu, T. Kanarsky, 2011, 2011 International Electron Devices Meeting.

Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

D. Corliss, T. Standaert, R. Wong, 2017, 2017 Symposium on VLSI Technology.

A 0.063 µm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

K. Maitra, P. Kulkarni, T. Yamashita, 2010, 2010 Symposium on VLSI Technology.

Comprehensive study of effective current variability and MOSFET parameter correlations in 14nm multi-fin SOI FINFETs

T. B. Hook, T. Yamashita, T. E. Standaert, 2013, 2013 IEEE International Electron Devices Meeting.

High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond

M. Khare, S. Luning, O. Faynot, 2013, 2013 IEEE International Electron Devices Meeting.

Two-level BEOL processing for rapid iteration in MRAM development

Yu Lu, William J. Gallagher, Solomon Assefa, 2006, IBM J. Res. Dev..

Implant approaches and challenges for 20nm node and beyond ETSOI devices

M. Khare, S. Luning, B. Haran, 2011, IEEE 2011 International SOI Conference.

Fabrication and characterization of MgO-based magnetic tunnel junctions for spin momentum transfer switching

William J. Gallagher, Solomon Assefa, Eugene J. O'Sullivan, 2007 .

Comparison of negative-ion and positive-ion-assisted etching of silicon

M. Khater, S. Kanakasabapathy, L. Overzet, 2001 .

Alternating fluxes of positive and negative ions from an ion–ion plasma

D. J. Economou, S. Kanakasabapathy, L. Overzet, 2001 .

A coupled two-sheath simulation of RF bias at high electronegativities

S. Kanakasabapathy, L. Overzet, 1998 .

FINFET technology featuring high mobility SiGe channel for 10nm and beyond

D. Liu, P. Oldiges, N. Loubet, 2016, 2016 IEEE Symposium on VLSI Technology.

A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

P. Oldiges, C. Park, N. Loubet, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Full metal gate with borderless contact for 14 nm and beyond

B. Haran, V. Narayanan, J. Bruley, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications

B. Jagannathan, N. Loubet, P. Kulkarni, 2010, Proceedings of 2010 International Symposium on VLSI Technology, System and Application.

Development of TiO2 containing hardmasks through plasma-enhanced atomic layer deposition

Indira Seshadri, Sivananda Kanakasabapathy, Luciana Meli, 2017 .

Development of TiO2 containing hardmasks through PEALD deposition

Indira Seshadri, Sivananda Kanakasabapathy, Luciana Meli, 2017, Advanced Lithography.

CMOS compatible MIM decoupling capacitor with reliable sub-nm EOT high-k stacks for the 7 nm node and beyond

T. Ando, V. Narayanan, J. Bruley, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond

K. Maitra, T. Yamashita, V. S. Basker, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

SiGe FinFET for practical logic libraries by mitigating local layout effect

Andreas Knorr, Jie Yang, John R. Sporre, 2017, 2017 Symposium on VLSI Technology.

A novel ALD SiBCN low-k spacer for parasitic capacitance reduction in FinFETs

S. Narasimha, J. Johnson, M. Khare, 2015, Symposium on VLSI Technology.

Impact of back bias on ultra-thin body and BOX (UTBB) devices

M. Vinet, T. Skotnicki, L. Grenouillet, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Wafer-scale oxide fusion bonding and wafer thinning development for 3D systems integration: Oxide fusion wafer bonding and wafer thinning development for TSV-last integration

R. Hannon, S. Kanakasabapathy, A. Upham, 2012, 2012 3rd IEEE International Workshop on Low Temperature Bonding for 3D Integration.

High-k metal gate fundamental learning and multi-Vt options for stacked nanosheet gate-all-around transistor

Nicolas Loubet, Tenko Yamashita, Sivananda Kanakasabapathy, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT

Jie Yang, Terence B. Hook, Andreas Knorr, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Sub-25nm FinFET with advanced fin formation and short channel effect engineering

K. Maitra, P. Kulkarni, T. Yamashita, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.