D. Suzuki

发表

The Glitch PUF: A New Delay-PUF Architecture Exploiting Glitch Shapes

Daisuke Suzuki, Koichi Shimizu, D. Suzuki, 2010, CHES.

Six-input lookup table circuit with 62% fewer transistors using nonvolatile logic-in-memory architecture with series/parallel-connected magnetic tunnel junctions

H. Ohno, T. Endoh, D. Suzuki, 2012 .

Design of a magnetic-tunnel-junction-oriented nonvolatile lookup table circuit with write-operation-minimized data shifting

Daisuke Suzuki, Takahiro Hanyu, D. Suzuki, 2018 .

A New Product-Sum Type Public Key Cryptosystem Based on Reduced Bases

M. Kasahara, D. Suzuki, R. Sakai, 2001 .

High-Speed Search System for PGP Passphrases

Daisuke Suzuki, Koichi Shimizu, Toyohiro Tsurumaru, 2008, CANS.

Evaluation Framework for Performance Limitation of Autonomous Systems under Sensor Attack

Daisuke Suzuki, Tsutomu Matsumoto, Tomoyuki Nagatsuka, 2021, SAFECOMP.

A Low-Cost Replica-Based Distance-Spoofing Attack on mmWave FMCW Radar

D. Suzuki, M. Nagata, N. Miura, 2019, ASHES@CCS.

Sensor CON-Fusion: Defeating Kalman Filter in Signal Injection Attack

Daisuke Suzuki, Takeshi Sugawara, Kazuo Sakiyama, 2018, AsiaCCS.

A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure

Daisuke Suzuki, Tetsuo Endoh, Takahiro Hanyu, 2014, IEICE Electronics Express.

Cost-Efficient Self-Terminated Write Driver for Spin-Transfer-Torque RAM and Logic

Daisuke Suzuki, Takahiro Hanyu, Masanori Natsui, 2014, IEEE Transactions on Magnetics.

Low-cost distance-spoofing attack on FMCW radar and its feasibility study on countermeasure

Makoto Nagata, Noriyuki Miura, Daisuke Suzuki, 2021, J. Cryptogr. Eng..

Bypassing Isolated Execution on RISC-V with Fault Injection

Naofumi Homma, Daisuke Suzuki, Rei Ueno, 2020, IACR Cryptol. ePrint Arch..

A Design Methodology for a DPA-Resistant Cryptographic LSI with RSL Techniques

Daisuke Suzuki, Minoru Saeki, Akashi Satoh, 2009, CHES.

How to Maximize the Potential of FPGA Resources for Modular Exponentiation

Daisuke Suzuki, D. Suzuki, 2007, CHES.

How to Maximize the Potential of FPGA-Based DSPs for Modular Exponentiation

Daisuke Suzuki, Tsutomu Matsumoto, Tsutomu Matsumoto, 2011, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Bypassing Isolated Execution on RISC-V using SC-Assisted FI and Its Countermeasure

D. Suzuki, N. Homma, Rei Ueno, 2021 .

Design and fabrication of a perpendicular magnetic tunnel junction based nonvolatile programmable switch achieving 40% less area using shared-control transistor structure.

Tetsuo Endoh, Takahiro Hanyu, Hiroaki Honjo, 2014, Journal of applied physics.

Design and evaluation of a 67% area-less 64-bit parallel reconfigurable 6-input nonvolatile logic element using domain-wall motion devices

Takahiro Hanyu, Daisuke Suzuki, Masanori Natsui, 2014 .

A 71%-Area-Reduced Six-Input Nonvolatile Lookup-Table Circuit Using a Three-Terminal Magnetic-Tunnel-Junction-Based Single-Ended Structure

Takahiro Hanyu, Daisuke Suzuki, Masanori Natsui, 2013 .

Design framework for an energy-efficient binary convolutional neural network accelerator based on nonvolatile logic

Takahiro Hanyu, Daisuke Suzuki, Akira Tamakoshi, 2021, Nonlinear Theory and Its Applications, IEICE.

Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style

Daisuke Suzuki, Minoru Saeki, D. Suzuki, 2006, CHES.

DPA Leakage Models for CMOS Logic Circuits

Daisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa, 2005, CHES.

Random Switching Logic: A Countermeasure against DPA based on Transition Probability

Daisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa, 2004, IACR Cryptol. ePrint Arch..

Reversing stealthy dopant-level circuits

Daisuke Suzuki, Takeshi Sugawara, Takeshi Fujino, 2014, Journal of Cryptographic Engineering.

Oscillator without a combinatorial loop and its threat to FPGA in data centre

Takeshi Sugawara, T. Nagatsuka, Suzuki Daisuke, 2019, Electronics Letters.

SAEB: A Lightweight Blockcipher-Based AEAD Mode of Operation

Mitsuru Matsui, Daisuke Suzuki, Yusuke Naito, 2018, IACR Trans. Cryptogr. Hardw. Embed. Syst..

Area-efficient LUT circuit design based on asymmetry of MTJ's current switching for a nonvolatile FPGA

T. Hanyu, M. Natsui, D. Suzuki, 2012, 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS).

An Optimized Implementation of AES-GCM for FPGA Acceleration Using High-Level Synthesis

Yang Li, Takeshi Sugawara, Daisuke Suzuki, 2020, 2020 IEEE 9th Global Conference on Consumer Electronics (GCCE).

Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating

Daisuke Suzuki, Shoji Ikeda, Tetsuo Endoh, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing

Daisuke Suzuki, Shoji Ikeda, Hiroki Koike, 2016, Proceedings of the IEEE.

TMR-logic-based LUT for quickly wake-up FPGA

T. Endoh, T. Hanyu, D. Suzuki, 2008, 2008 51st Midwest Symposium on Circuits and Systems.

12.1 An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz

Daisuke Suzuki, Shoji Ikeda, Hiroki Koike, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

Circuit optimization technique of nonvolatile logic-in-memory based lookup table circuits using magnetic tunnel junction devices

Daisuke Suzuki, Takahiro Hanyu, Takahiro Oka, 2019, Microelectron. J..

Design of a low-power nonvolatile flip-flop using three-terminal magnetic-tunnel-junction-based self-terminated mechanism

Daisuke Suzuki, Takahiro Hanyu, D. Suzuki, 2017 .

Challenge of MTJ-based nonvolatile logic-in-memory architecture for ultra low-power and highly dependable VLSI computing

Daisuke Suzuki, Shoji Ikeda, Tetsuo Endoh, 2015, 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Nonvolatile field-programmable gate array using 2-transistor–1-MTJ-cell-based multi-context array for power and area efficient dynamically reconfigurable logic

Takahiro Hanyu, Daisuke Suzuki, D. Suzuki, 2015 .

Magnetic-tunnel-junction based low-energy nonvolatile flip-flop using an area-efficient self-terminated write driver

Takahiro Hanyu, Daisuke Suzuki, D. Suzuki, 2015 .

Design of a cost-efficient controller for realizing a data-shift-minimized nonvolatile field-programmable gate array

Takahiro Hanyu, Daisuke Suzuki, D. Suzuki, 2020, Japanese Journal of Applied Physics.

Design of a highly reliable, high-speed MTJ-based lookup table circuit using fractured logic-in-memory structure

Takahiro Hanyu, Daisuke Suzuki, D. Suzuki, 2019, Japanese Journal of Applied Physics.

PUF as a sensor

Daisuke Suzuki, Takeshi Sugawara, Koichi Shimizu, 2015, 2015 IEEE 4th Global Conference on Consumer Electronics (GCCE).

Nonvolatile Field-Programmable Gate Array Using a Standard-Cell-Based Design Flow

Daisuke SUZUKI, Takahiro HANYU, D. Suzuki, 2021, IEICE Trans. Inf. Syst..

Design of an energy-efficient binarized convolutional neural network accelerator using a nonvolatile field-programmable gate array with only-once-write shifting

Takahiro Hanyu, Daisuke Suzuki, Takahiro Oka, 2021, Japanese Journal of Applied Physics.

Design and Evaluation of a Synthesizable Standard-Cell-Based Nonvolatile FPGA

Takahiro Hanyu, Daisuke Suzuki, D. Suzuki, 2020, 2020 IEEE 50th International Symposium on Multiple-Valued Logic (ISMVL).

A low-power MTJ-based nonvolatile FPGA using self-terminated logic-in-memory structure

Daisuke Suzuki, Takahiro Hanyu, D. Suzuki, 2016, 2016 26th International Conference on Field Programmable Logic and Applications (FPL).

Energy-Efficient and Highly-Reliable Nonvolatile FPGA Using Self-Terminated Power-Gating Scheme

Daisuke Suzuki, Takahiro Hanyu, D. Suzuki, 2016, 2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL).

Building Blocks to Use in Innovative Non-volatile FPGA Architecture Based on MTJs

Daisuke Suzuki, Zeljko Zilic, Takahiro Hanyu, 2012, 2012 IEEE Computer Society Annual Symposium on VLSI.

Three-terminal MTJ-based nonvolatile logic circuits with self-terminated writing mechanism for ultra-low-power VLSI processor

Daisuke Suzuki, Naoya Onizawa, Takahiro Hanyu, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure

Daisuke Suzuki, Shoji Ikeda, Tetsuo Endoh, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

Fabrication of a nonvolatile lookup-table circuit chip using magneto/semiconductor-hybrid structure for an immediate-power-up field programmable gate array

Daisuke Suzuki, Shoji Ikeda, Tetsuo Endoh, 2009, 2009 Symposium on VLSI Circuits.