Y. Zhu

发表

On the dynamic resistance and reliability of phase change memory

M. Breitwisch, G. Burr, Y. Shih, 2008, 2008 Symposium on VLSI Technology.

Novel Lithography-Independent Pore Phase Change Memory

M. Breitwisch, G. Burr, Yi-Chou Chen, 2007, 2007 IEEE Symposium on VLSI Technology.

Reliability study of a 128Mb phase change memory chip implemented with doped Ga-Sb-Ge with extraordinary thermal stability

C. Lam, W. Chien, H. Lung, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications

L. H. Vanamurth, D. Yang, T. Adam, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08µm2 SRAM cell

T. Adam, T. Standaert, M. Khare, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond

H. Sunamura, T. Yamamoto, B. Haran, 2010, 2010 Symposium on VLSI Technology.

Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drain

T. Adam, J. Holt, B. Haran, 2006, 2009 Symposium on VLSI Technology.

Assessment of fully-depleted planar CMOS for low power complex circuit operation

K. Tabakman, S. Wu, T. Kanarsky, 2011, 2011 International Electron Devices Meeting.

Ultrathin Strained-Ge Channel P-MOSFETs With High-$K$ /Metal Gate and Sub-1-nm Equivalent Oxide Thickness

J. Hoyt, Y. Zhu, G. Shahidi, 2012, IEEE Electron Device Letters.

Reduction of random telegraph noise in High-к / metal-gate stacks for 22 nm generation FETs

D. Frank, W. Haensch, M. Guillorn, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

A phase change memory cell with metallic surfactant layer as a resistance drift stabilizer

C. Lam, Y. Zhu, Y. Zhu, 2013, 2013 IEEE International Electron Devices Meeting.

Understanding short-term BTI behavior through comprehensive observation of gate-voltage dependence of RTN in highly scaled high-κ / metal-gate pFETs

D. Frank, W. Haensch, M. Guillorn, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

An ultra high endurance and thermally stable selector based on TeAsGeSiSe chalcogenides compatible with BEOL IC Integration for cross-point PCM

F. M. Lee, M. BrightSky, Y. Zhu, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Explore physical origins of resistance drift in phase change memory and its implication for drift-insensitive materials

Jing Li, H. L. Lung, Y. Zhu, 2011, 2011 International Electron Devices Meeting.

High performance and low leakage current InGaAs-on-silicon FinFETs with 20 nm gate length

M. Krishnan, E. Cartier, V. Narayanan, 2017, 2017 Symposium on VLSI Technology.

A 0.063 µm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

K. Maitra, P. Kulkarni, T. Yamashita, 2010, 2010 Symposium on VLSI Technology.

Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS

T. Nagumo, N. Loubet, W. Schwarzenbach, 2012, 2012 Symposium on VLSI Technology (VLSIT).

A method to maintain phase-change memory pre-coding data retention after high temperature solder bonding process in embedded systems

M. Breitwisch, S. Raoux, Y. Shih, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Write Strategies for 2 and 4-bit Multi-Level Phase-Change Memory

Y.C. Chen, M. Breitwisch, R. Bergmann, 2007, 2007 IEEE International Electron Devices Meeting.

ALD-based confined PCM with a metallic liner toward unlimited endurance

H. L. Lung, K. Suu, M. BrightSky, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Novel fast-switching and high-data retention phase-change memory based on new Ga-Sb-Ge material

H. L. Lung, M. BrightSky, Y. Zhu, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Racetrack memory cell array with integrated magnetic tunnel junction readout

P. Chevalier, W. J. Gallagher, E. J. O'Sullivan, 2011, 2011 International Electron Devices Meeting.

High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET

M. Vinet, L. Grenouillet, T. Nagumo, 2012, 2012 International Electron Devices Meeting.

Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications

B. Jagannathan, N. Loubet, P. Kulkarni, 2010, Proceedings of 2010 International Symposium on VLSI Technology, System and Application.

Statistical measurement of random telegraph noise and its impact in scaled-down high-κ/metal-gate MOSFETs

M. Kobayashi, M. Yamaoka, E. Leobandung, 2012, 2012 International Electron Devices Meeting.

Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond

K. Maitra, T. Yamashita, V. S. Basker, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

A novel inspection and annealing procedure to rejuvenate phase change memory from cycling-induced degradations for storage class memory applications

W. C. Chien, M. H. Lee, H. L. Lung, 2014, 2014 IEEE International Electron Devices Meeting.

Sharp Reduction of Contact Resistivities by Effective Schottky Barrier Lowering With Silicides as Diffusion Sources

W. Haensch, C. Lavoie, J. Newbury, 2010, IEEE Electron Device Letters.

Greater than 2-bits/cell MLC storage for ultra high density phase change memory using a novel sensing scheme

W. C. Chien, M. H. Lee, H. L. Lung, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).