Nizar Dahir

发表

Optimized task graph mapping on a many-core neuromorphic supercomputer

Indar Sugiarto, Pedro B. Campos, Nizar Dahir, 2017, 2017 IEEE High Performance Extreme Computing Conference (HPEC).

Minimizing power supply noise through harmonic mappings in networks-on-chip

Terrence S. T. Mak, Alexandre Yakovlev, Nizar Dahir, 2012, CODES+ISSS '12.

Design and Implementation of Dynamic Thermal-Adaptive Routing Strategy for Networks-on-Chip

Terrence S. T. Mak, Alexandre Yakovlev, Nizar Dahir, 2014, 2014 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing.

Plane-Balanced and Deadlock-Free Adaptive Routing for 3D Networks-on-Chip

Terrence Mak, Nizar Dahir, Petros Missailidis, 2012 .

Hybrid wire-surface wave architecture for one-to-many communication in networks-on-chip

Terrence S. T. Mak, Alexandre Yakovlev, Nizar Dahir, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Modeling and Tools for Power Supply Variations Analysis in Networks-on-Chip

Terrence S. T. Mak, Alexandre Yakovlev, Nizar Dahir, 2014, IEEE Transactions on Computers.

Highly Adaptive and Deadlock-Free Routing for 3D Networks-on-Chip

Terrence Mak, Nizar Dahir, Ra'ed Al-Dujaily, 2013 .

Fault tolerant task mapping on many-core arrays

Pedro B. Campos, Nizar Dahir, Gianluca Tempesti, 2016, 2016 IEEE Symposium Series on Computational Intelligence (SSCI).

XL-STaGe: A cross-layer scalable tool for graph generation, evaluation and implementation

Pedro B. Campos, Nizar Dahir, Gianluca Tempesti, 2016, 2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS).

Characterisation of feasibility regions in FPGAs under adaptive DVFS

Pedro B. Campos, Nizar Dahir, Gianluca Tempesti, 2015, 2015 25th International Conference on Field Programmable Logic and Applications (FPL).

Task Graph Mapping of General Purpose Applications on a Neuromorphic Platform

Indar Sugiarto, Nizar Dahir, Gianluca Tempesti, 2017 .

Communication centric on-chip power grid models for networks-on-chip

Terrence S. T. Mak, Alexandre Yakovlev, Nizar Dahir, 2011, 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip.

Adaptive Run-Time Thermal Balancing in 3D Network-on-Chip Systems Using Dynamic Programming Networks

Terrence Mak, Nizar Dahir, Ra'ed Al-Dujaily, 2012 .

Highly adaptive and deadlock-free routing for three-dimensional networks-on-chip

Terrence S. T. Mak, Alexandre Yakovlev, Nizar Dahir, 2013, IET Comput. Digit. Tech..

Deadlock-free and plane-balanced adaptive routing for 3D networks-on-chip

Terrence S. T. Mak, Alexandre Yakovlev, Nizar Dahir, 2012, NoCArc '12.

Network-on-Chip Multicast Architectures Using Hybrid Wire and Surface-Wave Interconnects

Terrence Mak, Nizar Dahir, Alex Yakovlev, 2018, IEEE Transactions on Emerging Topics in Computing.

LeAF: A low-overhead asymmetric frequency controller for NoC router interconnects

Pedro B. Campos, Nizar Dahir, Gianluca Tempesti, 2017, 2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

Thermal Optimization in Network-on-Chip-Based 3D Chip Multiprocessors Using Dynamic Programming Networks

Terrence S. T. Mak, Alexandre Yakovlev, Nizar Dahir, 2014, ACM Trans. Embed. Comput. Syst..

Dynamic programming-based runtime thermal management (DPRTM)

Terrence S. T. Mak, Alexandre Yakovlev, Nizar Dahir, 2013, ACM Trans. Design Autom. Electr. Syst..

Dynamic Thermal Optimization for 3D Many-Core Systems

Terrence Mak, Nizar Dahir, Ra'ed Al-Dujaily, 2017 .

Power density aware application mapping in mesh-based network-on-chip architecture: An evolutionary multi-objective approach

Terrence S. T. Mak, Alexandre Yakovlev, Nizar Dahir, 2021, Integr..