T. Sorsch

发表

Gate oxide reliability projection to the sub-2 nm regime

J. Bude, P. Diodato, A. Ghetti, 2000 .

The Vertical Replacement-Gate (VRG) MOSFET: a 50-nm vertical MOSFET with lithography-independent gate length

W. Lai, F. Baumann, D. Monroe, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

D. Tennant, J. Bude, K. Bourdelle, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

High-Density Solder Bump Interconnect for MEMS Hybrid Integration

W. Lai, T. Sorsch, V. Aksyuk, 2007, IEEE Transactions on Advanced Packaging.

The electronic structure at the atomic scale of ultrathin gate oxides

D. Muller, F. Baumann, T. Sorsch, 1999, Nature.

Si-doped aluminates for high temperature metal-gate CMOS: Zr-Al-Si-O, a novel gate dielectric for low power applications

R. V. van Dover, P. Silverman, T. Sorsch, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

50 nm vertical replacement-gate (VRG) nMOSFETs with ALD HfO2 and Al2O3 gate dielectrics

D. Muller, J. Grazul, P. Kalavade, 2001 .

MEMS thermal imager with optical readout

Nagesh R. Basavanhally, J. F. Miner, J. E. Bower, 2009 .

Flexible fabrication of large pixel count piston-tip-tilt mirror arrays for fast spatial light modulators

J. F. Miner, J. E. Bower, Raymond A. Cirelli, 2007 .

Small-Signal Performance and Modeling of sub-50nm nMOSFETs with f above 460-GHz.

T. Sorsch, G. Timp, J. Heng, 2008, Solid-state electronics.

Ultra-thin gate dielectrics: they break down, but do they fail?

D. Hwang, P.J. Silverman, F. Baumann, 1997, International Electron Devices Meeting. IEDM Technical Digest.

The role of native traps on the tunneling characteristics of ultrathin (1.5-3 nm) oxides

E. Sangiorgi, A. Ghetti, T. W. Sorsch, 1999 .

Ultra-thin, 1.0-3.0 nm, gate oxides for high performance sub-100 nm technology

K. Evans-Lutterodt, S. Moccio, J. Sapjeta, 1998, 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).

Low leakage, ultra-thin gate oxides for extremely high performance sub-100 nm nMOSFETs

A. Agarwal, J. Jackson, F. Klemens, 1997, International Electron Devices Meeting. IEDM Technical Digest.

Low voltage tunneling in ultra-thin oxides: a monitor for interface states and degradation

E. Sangiorgi, A. Ghetti, J. Bude, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

COM2 enhanced graded base SiGe technology for high speed applications

P. Smith, R. Johnson, T. Sorsch, 2002, 2002 IEEE MTT-S International Microwave Symposium Digest (Cat. No.02CH37278).

Oxidation of Si beneath thin SiO2 layers during exposure to HBr/O2 plasmas, investigated by vacuum transfer x-ray photoelectron spectroscopy

V. M. Donnelly, F. Baumann, T. Sorsch, 1999 .

Isotopic labeling studies of interactions of nitric oxide and nitrous oxide with ultrathin oxynitride layers on silicon

Martin L. Green, E. Gusev, T. Sorsch, 2000 .

A novel, nanocrystal (nc) based non-volatile memory device

H. Atwater, J. Bude, T. Sorsch, 2000 .

Thermal Routes to Ultrathin Oxynitrides

E. P. Gusev, Leonard C. Feldman, D. Brasen, 1998 .

Ultrathin SiOxNy by rapid thermal heating of silicon in N2 at T=760–1050 °C

E. P. Gusev, Leonard C. Feldman, Martin L. Green, 1997 .

Nanopores in solid-state membranes engineered for single molecule detection

T. Sorsch, G. Timp, F. Klemens, 2010, Nanotechnology.

Nucleation and growth of atomic layer deposited HfO2 gate dielectric layers on chemical oxide (Si–O–H) and thermal oxide (SiO2 or Si–O–N) underlayers

Wilfried Vandervorst, Martin A. Green, David A. Muller, 2002 .

Beyond the gene chip

Aleksei Aksimentiev, Klaus Schulten, William M. Mansfield, 2005, Bell Labs Technical Journal.

Relationship between Interfacial Roughness and Dielectric Reliability for Silicon Oxynitride Gate Dielectrics Processed with Nitric Oxide

Martin L. Green, Jane P. Chang, B. Weir, 1999 .

Understanding the limits of ultrathin SiO 2 and Si-O-N gate dielectrics for sub-50 nm CMOS

Martin L. Green, D. Muller, B. Weir, 1999 .

Rapid thermal processing of silicon wafers with emissivity patterns

T. Sorsch, N. Ravindra, E. Ferry, 2006 .

Monolithic fringe-field-activated crystalline silicon tilting-mirror devices

J. E. Bower, Dan M. Marom, Chorng-Ping Chang, 2003 .

Multi-component high-K gate dielectrics for the silicon industry

Fred P. Klemens, Martin L. Green, Glen D. Wilk, 2001 .

Tunneling into interface states as reliability monitor for ultrathin oxides

Enrico Sangiorgi, A. Ghetti, J. Bude, 2000 .

Progress toward 10 nm CMOS devices

A. Ghetti, P. Silverman, D.M. Tennant, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

Gate oxides in 50 nm devices: thickness uniformity improves projected reliability

A. Ghetti, J. Madic, J.D. Bude, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

Compact spectral pulse shaping using hybrid planar lightwave circuit and free-space optics with MEMS piston micromirrors and spectrogram feedback control

C.R. Doerr, M. Cappuzzo, L. Gomez, 2004, The 17th Annual Meeting of the IEEELasers and Electro-Optics Society, 2004. LEOS 2004..

50 nm vertical replacement-gate (VRG) nMOSFETs with ALD HfO/sub 2/ and Al/sub 2/O/sub 3/ gate dielectrics

T. Nigam, A. Kornblit, M.R. Baker, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

The relentless march of the MOSFET gate oxide thickness to zero

Donald M. Tennant, A. Kornblit, Gregory Timp, 2000 .

Progress toward a 30 nm silicon metal–oxide–semiconductor gate technology

Martin L. Green, D. Tennant, T. Sorsch, 1999 .

The detection of DNA using a silicon nanopore

T. Sorsch, T. Sorsch, G. Timp, 2003, IEEE International Electron Devices Meeting 2003.

Ultrashallow p+-n junctions formed by diffusion from an RTCVD-deposited B:Ge layer

Jeffrey Bokor, T. W. Sorsch, D. J. Eaglesham, 1994, Other Conferences.