H. Hwang

23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme

Jonghyuk Kim, Hoon Lee, Young Choi, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 $\times$ 128 I/Os Using TSV Based Stacking

Young-Hyun Jun, Byongwook Na, Donghyuk Lee, 2011, IEEE Journal of Solid-State Circuits.

A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking

Young-Hyun Jun, Byongwook Na, Donghyuk Lee, 2011, 2011 IEEE International Solid-State Circuits Conference.

A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques

Dongkeon Lee, Dukha Park, Byongwook Na, 2020, IEEE Journal of Solid-State Circuits.

23.1 A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power

Sukhyun Lim, Jin-Hun Jang, Dukha Park, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).