S. Hyun

23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme

Jonghyuk Kim, Hoon Lee, Young Choi, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

1.2V 1.6Gb/s 56nm 6F2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture

Young-Hyun Jun, Jung-Hwan Choi, Byungchul Kim, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

Bulk-Si photonics technology for DRAM interface [Invited]

Dong-Hyun Kim, B. Kuh, G. Jeong, 2014 .

Si-based optical I/O for optical memory interface

Chilhee Chung, Kwanghyun Lee, Jinwoo Choi, 2012, Other Conferences.

A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme

Jun-Seok Park, Jongeun Lee, Kyomin Sohn, 2012, IEEE Journal of Solid-State Circuits.

A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process

Hoon Shin, Young Choi, Inkyu Moon, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

23.1 A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power

Sukhyun Lim, Jin-Hun Jang, Dukha Park, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage–Frequency Scaling in LPDDR4 SDRAM

Dong-Hun Lee, Junha Lee, Jung-Hwan Choi, 2018, IEEE Journal of Solid-State Circuits.