Indal Song

23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme

Jonghyuk Kim, Hoon Lee, Young Choi, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

17.7 A digital DLL with hybrid DCC using 2-step duty error extraction and 180° phase aligner for 2.67Gb/S/pin 16Gb 4-H stack DDR4 SDRAM with TSVs

Jung-Hwan Choi, Seok-Ho Lee, Hundai Choi, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme

Jun-Seok Park, Jongeun Lee, Kyomin Sohn, 2012, IEEE Journal of Solid-State Circuits.

A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme

Young Choi, Jung-Hwan Choi, Jongeun Lee, 2012, 2012 IEEE International Solid-State Circuits Conference.

Design technologies for a 1.2V 2.4Gb/s/pin high capacity DDR4 SDRAM with TSVs

Reum Oh, Yun-Sang Lee, Byunghyun Lee, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage–Frequency Scaling in LPDDR4 SDRAM

Dong-Hun Lee, Junha Lee, Jung-Hwan Choi, 2018, IEEE Journal of Solid-State Circuits.