J. Choi

发表

23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme

Jonghyuk Kim, Hoon Lee, Young Choi, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

17.7 A digital DLL with hybrid DCC using 2-step duty error extraction and 180° phase aligner for 2.67Gb/S/pin 16Gb 4-H stack DDR4 SDRAM with TSVs

Jung-Hwan Choi, Seok-Ho Lee, Hundai Choi, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

1.2V 1.6Gb/s 56nm 6F2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture

Young-Hyun Jun, Jung-Hwan Choi, Byungchul Kim, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

Bulk-Si photonics technology for DRAM interface [Invited]

Dong-Hyun Kim, B. Kuh, G. Jeong, 2014 .

Leakage Power Dependent Temperature Estimation to Predict Thermal Runaway in FinFET Circuits

J. Murthy, K. Roy, J. Choi, 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

A 4-Gb/s/pin low-power memory I/O interface using 4-level simultaneous bi-directional signaling

Jin-Hyun Kim, Hong-Sun Hwang, Woo-Seop Kim, 2005, IEEE J. Solid State Circuits.

The effect of process variation on device temperature in FinFET circuits

Kaushik Roy, Jayathi Y. Murthy, Jung Hwan Choi, 2007, ICCAD 2007.

The morphological degradation mechanism of the TiSi2/Si structure

H. S. Kim, J. Choi, S. I. Lee, 1993 .

Low-k film damage-resistant CO chemistry-based ash process for low-k/Cu interconnection in flash memory devices

J. Choi, D. Kim, W. Park, 2008 .

Ti-silicide with improved thermal stability using silicidation through oxide on amorphous silicon substrates

J. Choi, Sung-Goon Kang, J. Lee, 1993 .

A field-emission display with a self-focus cathode electrode

Sung-Wook Kang, J. M. Kim, C. G. Lee, 2003 .

A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme

Jun-Seok Park, Jongeun Lee, Kyomin Sohn, 2012, IEEE Journal of Solid-State Circuits.

A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme

Young Choi, Jung-Hwan Choi, Jongeun Lee, 2012, 2012 IEEE International Solid-State Circuits Conference.

A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process

Hoon Shin, Young Choi, Inkyu Moon, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology

Young-Hyun Jun, Dukha Park, Sooho Cha, 2009, IEEE Journal of Solid-State Circuits.

18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution

Reum Oh, Dong-Hak Shin, Jae-Hun Jung, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

A process variation aware low power synthesis methodology for fixed-point FIR filters

Kaushik Roy, Nilanjan Banerjee, Jung Hwan Choi, 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

Variation-Aware Low-Power Synthesis Methodology for Fixed-Point FIR Filters

Kaushik Roy, Nilanjan Banerjee, Jung Hwan Choi, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices

Hyun-Soo Park, Hyuk-Jun Kwon, Jong-Ho Lee, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

O2C: occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessors

Kaushik Roy, Swaroop Ghosh, Patrick Ndai, 2008, Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08).

A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution

G. Jin, Yong-Cheol Bae, J. Choi, 2017, IEEE Journal of Solid-State Circuits.

Design technologies for a 1.2V 2.4Gb/s/pin high capacity DDR4 SDRAM with TSVs

Reum Oh, Yun-Sang Lee, Byunghyun Lee, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

A Sub-1.0V 20nm 5Gb/s/pin post-LPDDR3 I/O interface with Low Voltage-Swing Terminated Logic and adaptive calibration scheme for mobile application

Jung-Hwan Choi, Min-Ho Park, Kwang-Il Park, 2013, 2013 Symposium on VLSI Circuits.

23.1 A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power

Sukhyun Lim, Jin-Hun Jang, Dukha Park, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage–Frequency Scaling in LPDDR4 SDRAM

Dong-Hun Lee, Junha Lee, Jung-Hwan Choi, 2018, IEEE Journal of Solid-State Circuits.

A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking

Yong Jae Lee, Hyun-Soo Park, Hyuk-Jun Kwon, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

13.1 A 1Tb 4b/cell NAND Flash Memory with tPROG=2ms, tR=110µs and 1.2Gb/s High-Speed IO Rate

Jiyoon Park, Dae-Seok Byeon, Jisu Kim, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

Performance Evaluation of Vehicle Network Protocols for X-By-Wire Using Simulation

Man Ho Kim, Suk Lee, Kyung Chang Lee, 2005 .