V. Vedula

Security verification of 3rd party intellectual property cores for information leakage

R. Karri, V. Vedula, J. Rajendran, 2015 .

Formal verification using bounded model checking: SAT versus sequential ATPG engines

Daniel G. Saab, Jacob A. Abraham, Vivekananda M. Vedula, 2003, 16th International Conference on VLSI Design, 2003. Proceedings..

Verifying properties using sequential ATPG [IC design]

Daniel G. Saab, Jacob A. Abraham, Vivekananda M. Vedula, 2002, Proceedings. International Test Conference.

Verifying Properties Using Sequential ATPG

D. G. Saab, Vivekananda M. Vedula, Jacob A. Abraham, 2002 .

Program slicing for hierarchical test generation

Jacob A. Abraham, Vivekananda M. Vedula, Jayanta Bhadra, 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

Automatic Constraint Based Test Generation for Behavioral HDL Models

V. Kamakoti, Vivekananda M. Vedula, Vishnu Vardhan Reddy Konda, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Detecting malicious modifications of data in third-party intellectual property cores

Jeyavijayan Rajendran, Ramesh Karri, Vivekananda Vedula, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Formal Security Verification of Third Party Intellectual Property Cores for Information Leakage

Jeyavijayan Rajendran, Ramesh Karri, Vivekananda Vedula, 2016, 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID).