Satyanand Nalam

发表

Limits of bias based assist methods in nano-scale 6T SRAM

Jiajing Wang, Benton H. Calhoun, Randy W. Mann, 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

5T SRAM With Asymmetric Sizing for Improved Read Stability

Benton H. Calhoun, Satyanand Nalam, B. Calhoun, 2011, IEEE Journal of Solid-State Circuits.

Session 17 Overview: Embedded Memory and DRAM I/O

Zheng Guo, Kevin Zhang, Satyanand Nalam, 2015 .

Virtual prototyper (ViPro): An early design space exploration and optimization tool for SRAM designers

Benton H. Calhoun, Ken Mai, Mudit Bhargava, 2010, Design Automation Conference.

Circuit and CAD Solutions for Optimal SRAM Design in Nanoscale CMOS

B. Calhoun, Satyanand Nalam, 2010 .

Analyzing static and dynamic write margin for nanometer SRAMs

Jiajing Wang, Benton H. Calhoun, Satyanand Nalam, 2008, Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08).

A 23.6Mb/mm2 SRAM in 10nm FinFET technology with pulsed PMOS TVC and stepped-WL for low-voltage applications

Xiaofei Wang, Zheng Guo, Daeyeon Kim, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

Sub-550mV SRAM Design in 22nm FinFET Low Power (22FFL) Technology with Self-Induced Collapse Write Assist

Satyanand Nalam, J. Wiedemer, Daeyeon Kim, 2018, 2018 IEEE Symposium on VLSI Technology.

5.6 Mb/mm $^{2}$ 1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology

Jaydeep Kulkarni, Eric Karl, Kevin Zhang, 2017, IEEE Journal of Solid-State Circuits.

Impact of circuit assist methods on margin and performance in 6T SRAM

Jiajing Wang, Benton H. Calhoun, Harold Pilo, 2010 .

A 0.6 V, 1.5 GHz 84 Mb SRAM in 14 nm FinFET CMOS Technology With Capacitive Charge-Sharing Write Assist Circuitry

Xiaofei Wang, Zheng Guo, John Keane, 2016, IEEE Journal of Solid-State Circuits.

17.1 A 0.6V 1.5GHz 84Mb SRAM design in 14nm FinFET CMOS technology

Zheng Guo, John Keane, Daeyeon Kim, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

Asymmetric sizing in a 45nm 5T SRAM to improve read stability over 6T

Benton H. Calhoun, Satyanand Nalam, B. Calhoun, 2009, 2009 IEEE Custom Integrated Circuits Conference.