V. Ku

High performance and low power transistors integrated in 65nm bulk CMOS technology

M. Weybright, A. Vayshenker, A. Steegen, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

High speed 45nm gate length CMOSFETs integrated into a 90nm bulk technology incorporating strain engineering

D. Lea, E. Nowak, S. Yang, 2003, IEEE International Electron Devices Meeting 2003.

Triple-self-aligned, planar double-gate MOSFETs: devices and circuits

J. Treichler, K. Guarini, G. Cohen, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Device design considerations for ultra-thin SOI MOSFETs

V. Narayanan, M. Steen, R. Jammy, 2003, IEEE International Electron Devices Meeting 2003.

Two gates are better than one [double-gate MOSFET process]

J. Benedict, J. Treichler, H.-S.P. Wong, 2003, IEEE Circuits and Devices Magazine.

65nm cmos technology for low power applications

M. Sherony, T. Schiml, A. Cowley, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

High performance cmos bulk technology using direct silicon bond (dsb) mixed crystal orientation substrates

Chun-Yung Sung, Zhijiong Luo, Haizhou Yin, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..