F. Jamin

High performance and low power transistors integrated in 65nm bulk CMOS technology

M. Weybright, A. Vayshenker, A. Steegen, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Extreme scaling with ultra-thin Si channel MOSFETs

H.-S.P. Wong, Ying Zhang, Leathen Shi, 2002, Digest. International Electron Devices Meeting,.

Monolithically integrated silicon nitride platform

Tymon Barwicz, Takako Hirokawa, Danhao Ma, 2021, 2021 Optical Fiber Communications Conference and Exhibition (OFC).

65nm cmos technology for low power applications

M. Sherony, T. Schiml, A. Cowley, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing

G. Burbach, D. Greenlaw, S.F. Huang, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..