D. Park

High performance and low power transistors integrated in 65nm bulk CMOS technology

M. Weybright, A. Vayshenker, A. Steegen, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Voltage and temperature dependence of random telegraph noise in highly scaled HKMG ETSOI nFETs and its impact on logic delay uncertainty

D. Frank, D. Park, M. Yamaoka, 2012, 2012 Symposium on VLSI Technology (VLSIT).

High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing

Syed Muhammad Zain Zafar, M. Hargrove, C. Ouyang, 2007, 2007 IEEE Symposium on VLSI Technology.

Stress dependence and poly-pitch scaling characteristics of (110) PMOS drive current

S. Narasimha, A. Waite, J. Johnson, 2007, 2007 IEEE Symposium on VLSI Technology.

True 7nm Platform Technology featuring Smallest FinFET and Smallest SRAM cell by EUV, Special Constructs and 3rd Generation Single Diffusion Break

S. Jung, D. Park, S. Maeda, 2018, 2018 IEEE Symposium on VLSI Technology.

Temperature Dependent Study of Random Telegraph Noise in Gate-All-Around PMOS Silicon Nanowire Field-Effect Transistors

G. Jin, D. Park, K. Yeo, 2010, IEEE Transactions on Nanotechnology.

Subthreshold Degradation of Gate-all-Around Silicon Nanowire Field-Effect Transistors: Effect of Interface Trap Charge

S. J. Lee, G. Jin, J. Rieh, 2011, IEEE Electron Device Letters.

Statistical measurement of random telegraph noise and its impact in scaled-down high-κ/metal-gate MOSFETs

M. Kobayashi, M. Yamaoka, E. Leobandung, 2012, 2012 International Electron Devices Meeting.

High Performance Transistors Featured in an Aggressively Scaled 45nm Bulk CMOS Technology

J. Sudijono, H. Utomo, M. Ieong, 2007, 2007 IEEE Symposium on VLSI Technology.