J. Ku

发表

High performance and low power transistors integrated in 65nm bulk CMOS technology

M. Weybright, A. Vayshenker, A. Steegen, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process

X. Chen, M. Khare, D. Tekleab, 2008, 2008 Symposium on VLSI Technology.

Stress Proximity Technique for Performance Improvement with Dual Stress Liner at 45nm Technology and Beyond

M. Belyansky, X. Chen, R. Amos, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Mass-productive ultra-low temperature ALD SiO/sub 2/ process promising for sub-90 nm memory and logic devices

Ho-Kyu Kang, J. Ku, N. Lee, 2002, Digest. International Electron Devices Meeting,.

Ex Situ and in Situ Methods for Oxide and Carbon Removal from AlN and GaN Surfaces

J. Ku, R. Davis, R. Nemanich, 1995 .

Characteristics of ZrO2 Films with Al and Pt Gate Electrodes

J. Ku, S. Nam, D. Ko, 2003 .

Study of ZrO2 thin films for gate oxide applications

J. Ku, S. Nam, Hoo-Jeong Lee, 2001 .

Competitive and cost effective high-k based 28nm CMOS technology for low power applications

J. Bonnouvrier, R. Augur, F. Arnaud, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Thermal stability of Al- and Zr-doped HfO2 thin films grown by direct current magnetron sputtering

J. Ku, Hyoungsub Kim, D. Ko, 2005 .

Removal of fluorine from a Si (100) surface by a remote RF hydrogen plasma

J. Ku, R. Nemanich, S. King, 1995 .

Annealing effects of aluminum silicate films grown on Si(100)

J. Ku, H. C. Kang, M. Cho, 2002 .

The effects of Ta on the formation of Ni-silicide in Ni0.95xTax0.05/Si systems

J. Ku, Si-young Choi, D. Ko, 2004 .

Hydrogen evolution from strained SixGe1−x(100)2×1:H surfaces

J. Ku, R. Nemanich, 1996 .

The Schottky barrier of Co on strained and unstrained SixGe1−x alloys

J. Ku, R. Nemanich, 1996 .

High Thermal Stability of Ni Monosilicide from Ni-Ta Alloy Films on Si(100)

J. Ku, Si-young Choi, D. Ko, 2003 .

Effect of a noble annealing system on nickel silicide formation

U. Chung, J. Moon, B. Ryu, 2004, 12th IEEE International Conference on Advanced Thermal Processing of Semiconductors, 2004. RTP 2004..

Thermally robust Ta-doped Ni SALICIDE process promising for sub-50 nm CMOSFETs

S. Choi, J. Ku, N. Lee, 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

65nm cmos technology for low power applications

M. Sherony, T. Schiml, A. Cowley, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Interfacial characteristics of HfO2 films grown on strained Si0.7Ge0.3 by atomic-layer deposition

P. McIntyre, J. Ku, N. Lee, 2004 .

A study on the microstructure and electrical properties of CeO2 thin films for gate dielectric applications

J. Ku, S. Nam, Hoo-Jeong Lee, 2001 .

Ultimate solution for low thermal budget gate spacer and etch stopper to retard short channel effect in sub-90 nm devices

Ho-Kyu Kang, J. Ku, N. Lee, 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

Novel High-Performance Analog Devices for Advanced Low-Power High-k Metal Gate Complementary Metal–Oxide–Semiconductor Technology

F. S. Johnson, R. Wachnik, K. Barla, 2011 .

Impact of mechanical stress engineering on flicker noise characteristics

S. Maeda, You-Seung Jin, Jung-A Choi, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

Gate leakage current reduction and improved reliability with an ultra-thin Ti layer for low-power applications

J. Ku, P. Choi, Byoungdeog Choi, 2020 .

Extreamly Advanced Cu Interconnect with Selective ALD Barrier for High Performance Logic Device

J. Ku, R. Kim, Chi-Seon Park, 2023, 2023 IEEE International Interconnect Technology Conference (IITC) and IEEE Materials for Advanced Metallization Conference (MAM)(IITC/MAM).

High Performance Transistors Featured in an Aggressively Scaled 45nm Bulk CMOS Technology

J. Sudijono, H. Utomo, M. Ieong, 2007, 2007 IEEE Symposium on VLSI Technology.

17.1 A 10nm FinFET 128Mb SRAM with assist adjustment system for power, performance, and area optimization

Taejoong Song, Gyu-Hong Kim, Sunhom Steve Paak, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

New layout dependency in high-k/Metal Gate MOSFETs

M. Sherony, F. Arnaud, F. Matsuoka, 2011, 2011 International Electron Devices Meeting.

Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications

Y. S. Nam, J. H. Lee, K. H. Lee, 2016, 2016 IEEE Symposium on VLSI Technology.

Physical and electrical degradation of ZrO2 thin films with aluminum electrodes

J. Ku, S. Nam, D. Ko, 2003 .