A. Bhavnagarwala

发表

Fluctuation limits & scaling opportunities for CMOS SRAM cells

S. Kosonocky, R. Mann, R. Mann, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

A pico-joule class, 1 GHz, 32 KByte/spl times/64 b DSP SRAM with self reverse bias

M. Immediato, S. Kosonocky, A. Bhavnagarwala, 2003, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).

A transregional CMOS SRAM with single, logic V/sub DD/ and dynamic power rails

S. Kosonocky, A. Bhavnagarwala, R. Joshi, 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

The impact of gate-oxide breakdown on SRAM stability

J. Stathis, B. Linder, A. Bhavnagarwala, 2002, IEEE Electron Device Letters.

The impact of intrinsic device fluctuations on CMOS SRAM cell stability

J. Meindl, Xinghai Tang, A. Bhavnagarwala, 2001, IEEE J. Solid State Circuits.

Interconnect-centric array architectures for minimum SRAM access time

Azeez J. Bhavnagarwala, James D. Meindl, Stephen V. Kosonocky, 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.

Circuit techniques for low-power CMOS GSI

Vivek De, Azeez J. Bhavnagarwala, Blanca Austin, 1996, ISLPED '96.

Projections for high performance, minimum power CMOS ASIC technologies: 1998-2010

James D. Meindl, B. L. Austin, A. J. Bhavnagarwala, 1997, Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334).

Optimal circuit design for low power CMOS GSI

J. Meindl, B. Austin, A. Bhavnagarwala, 1996, Proceedings Ninth Annual IEEE International ASIC Conference and Exhibit.

Impact of interconnect parameter variations on wire-tree delay

James D. Meindl, A. Kapoor, A. J. Bhavnagarwala, 2000, 2000 5th International Workshop on Statistical Metrology (Cat.No.00TH8489.

A Sub-600mV, Fluctuation tolerant 65nm CMOS SRAM Array with Dynamic Cell Biasing

S. Kosonocky, Yuen Chan, K. Stawiasz, 2007, 2007 IEEE Symposium on VLSI Circuits.

A minimum total power methodology for projecting limits on CMOS GSI

Keith A. Bowman, Azeez J. Bhavnagarwala, Blanca Austin, 2000, IEEE Trans. Very Large Scale Integr. Syst..

CMOS system-on-a-chip voltage scaling beyond 50nm

Azeez J. Bhavnagarwala, Blanca Austin, James D. Meindl, 2000, ACM Great Lakes Symposium on VLSI.

A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing

C. Radens, S.P. Kowalczyk, Yuen Chan, 2008, IEEE Journal of Solid-State Circuits.