C. Lin

A 32nm CMOS Low Power SoC Platform Technology for Foundry Applications with Functional High Density SRAM

Shien-Yang Wu, M. Chiang, J. Liaw, 2007, 2007 IEEE International Electron Devices Meeting.

A highly manufacturable 28nm CMOS low power platform technology with fully functional 64Mb SRAM using dual/tripe gate oxide process

C.C. Chen, Shien-Yang Wu, S.Y. Chang, 2006, 2009 Symposium on VLSI Technology.

A 7nm CMOS platform technology featuring 4th generation FinFET transistors with a 0.027um2 high density 6-T SRAM cell for mobile SoC applications

C.C. Chen, Shien-Yang Wu, S.Y. Chang, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

A Simulation Study of Oxide Thickness Effect on the Performance of SiGe HBTs with SOI Structure

C. Lin, S. Chang, W.-C. Wang, 2007, 2007 IEEE Conference on Electron Devices and Solid-State Circuits.

Critical Process Features Enabling Aggressive Contacted Gate Pitch Scaling for 3nm CMOS Technology and Beyond

C. O. Chui, M. Chiang, J. Liaw, 2022, 2022 International Electron Devices Meeting (IEDM).

A 3nm CMOS FinFlex™ Platform Technology with Enhanced Power Efficiency and Performance for Mobile SoC and High Performance Computing Applications

Shien-Yang Wu, M. Chiang, V. Chang, 2022, 2022 International Electron Devices Meeting (IEDM).