Y. Takasu

Scaling of 32nm low power SRAM with high-K metal gate

R. Wong, X. Chen, M. Khare, 2008, 2008 IEEE International Electron Devices Meeting.

A 45nm High Performance Bulk Logic Platform Technology (CMOS6) using Ultra High NA(1.07) Immersion Lithography with Hybrid Dual-Damascene Structure and Porous Low-k BEOL

S. Takahashi, S. Yamada, S. Muramatsu, 2006, 2006 International Electron Devices Meeting.

The effect of nitrogen addition during high-rate homoepitaxial growth of diamond by microwave plasma CVD

Y. Takasu, N. Fujimori, A. Chayahara, 2004 .

New layout dependency in high-k/Metal Gate MOSFETs

M. Sherony, F. Arnaud, F. Matsuoka, 2011, 2011 International Electron Devices Meeting.