S. Samavedam

发表

Scaling of 32nm low power SRAM with high-K metal gate

R. Wong, X. Chen, M. Khare, 2008, 2008 IEEE International Electron Devices Meeting.

Monolithic integration of III-V materials and devices on silicon

Steven A. Ringel, Mayank T. Bulsara, Eugene A. Fitzgerald, 1999, Photonics West.

Variation improvement for manufacturable FINFET technology

Xing Zhang, Rohit Pal, Mitsuhiro Togo, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications

S. Narasimha, M. Hargrove, R. Pal, 2011, 2011 International Electron Devices Meeting.

High performance 32nm SOI CMOS with high-k/metal gate and 0.149µm2 SRAM and ultra low-k back end with eleven levels of copper

M. Belyansky, L. Black, J. Holt, 2006, 2009 Symposium on VLSI Technology.

A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process

X. Chen, M. Khare, D. Tekleab, 2008, 2008 Symposium on VLSI Technology.

Controlling threading dislocation densities in Ge on Si using graded SiGe layers and chemical-mechanical polishing

Thomas A. Langdo, Christopher W. Leitz, Eugene A. Fitzgerald, 1998 .

Analysis of TID Process, Geometry, and Bias Condition Dependence in 14-nm FinFETs and Implications for RF and SRAM Performance

J. S. Kauppila, D. R. Ball, T. D. Haeffner, 2017, IEEE Transactions on Nuclear Science.

Sub-quarter micron Si-gate CMOS with ZrO/sub 2/ gate dielectric

D. Gilmer, T. Ma, S. Samavedam, 2001, 2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517).

Compatibility of Silicon gates with hafnium-based gate dielectrics

Raghaw Rai, Rama I. Hegde, L. Prabhu, 2003 .

Compatibility of polycrystalline silicon gate deposition with HfO2 and Al2O3/HfO2 gate dielectrics

Raghaw Rai, Rama I. Hegde, L. Prabhu, 2002 .

14-nm FinFET Technology for Analog and RF Applications

J. Watts, Jagar Singh, A. Bellaouar, 2018, IEEE Transactions on Electron Devices.

Strained SiGe Channels for Band-Edge PMOS Threshold Voltages With Metal Gates and High- $k$ Dielectrics

C. Capasso, B. Winstead, D. Tekleab, 2010, IEEE Transactions on Electron Devices.

Influence of strain on semiconductor thin film epitaxy

Ya-Hong Xie, E. A. Fitzgerald, E. Fitzgerald, 1997 .

SiGe-Channel Confinement Effects for Short-Channel PFETs With Nonbandedge Gate Workfunctions

D. Tekleab, S. Samavedam, B. Winstead, 2007, IEEE Electron Device Letters.

High-quality germanium photodiodes integrated on silicon substrates using optimized relaxed graded buffers

Thomas A. Langdo, Eugene A. Fitzgerald, E. Fitzgerald, 1998 .

Dislocations in Relaxed SiGe/Si Heterostructures

E. Fitzgerald, M. Bulsara, M. Currie, 1999 .

Line, point and surface defect morphology of graded, relaxed GeSi alloys on Si substrates

E. Fitzgerald, S. Samavedam, 1997 .

Influence of substrate off-cut on the defect structure in relaxed graded Si-Ge/Si layers

E. Fitzgerald, F. Romanato, S. Samavedam, 1996 .

Quantitative model of CMOS inverter chain ring oscillator's effective capacitance and its improvements in 14nm FinFET technology

S. Samavedam, S. Mun, J. Ciavatti, 2018, 2018 IEEE International Conference on Microelectronic Test Structures (ICMTS).

LASER Anneal to Enable Ultimate CMOS Scaling with PMOS Band Edge Metal Gate/High-K Stacks

D. Gilmer, S. Samavedam, J. Schaeffer, 2006, 2006 European Solid-State Device Research Conference.

High Quality Germanium Photodiodes on Silicon Substrates Using an Intermediate Chemical Mechanical Polishing Step

E. Fitzgerald, M. Currie, S. Samavedam, 1997 .

Fermi Level Pinning with Sub-monolayer MeOx and Metal Gates

D. Gilmer, S. Samavedam, A. Demkov, 2003 .

Elevated source drain devices using silicon selective epitaxial growth

Philip J. Tobin, Olubunmi O. Adetutu, A. Dip, 2000 .

Defect structures in silicon merged epitaxial lateral overgrowth

S. Samavedam, G. Neudeck, A. Kabir, 1995 .

Pulsed laser-ablation deposition of thin films of molybdenum silicide and its properties as a conducting barrier for ferroelectric random-access memory technology

S. Samavedam, S. Choopun, R. Sharma, 1999 .

Contributions to the effective work function of platinum on hafnium dioxide

B. E. White, Philip J. Tobin, S. Samavedam, 2004 .

Relaxed template for fabricating regularly distributed quantum dot arrays

Mayank T. Bulsara, Thomas A. Langdo, Eugene A. Fitzgerald, 1997 .

Novel dislocation structure and surface morphology effects in relaxed Ge/Si-Ge(graded)/Si structures

E. Fitzgerald, S. Samavedam, 1997 .

Metal gate MOSFETs with HfO/sub 2/ gate dielectric

P. Abramowitz, P.J. Tobin, E. Luckowski, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

Dual-metal gate CMOS with HfO2 gate dielectric

P. Abramowitz, J. Conner, E. Luckowski, 2002, Digest. International Electron Devices Meeting,.

Relaxation of strained Si layers grown on SiGe buffers

Philip J. Tobin, A. Dip, S. Samavedam, 1999 .

Impact of aggressive fin width scaling on FinFET device characteristics

J. G. Lee, K. Tabakman, S. Samavedam, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Toward device-quality GaAs growth by molecular beam epitaxy on offcut Ge/Si1−xGex/Si substrates

Steven A. Ringel, S. M. Ting, Thomas A. Langdo, 1998 .

Hafnium zirconate gate dielectric for advanced gate stack applications

S. Samavedam, R. Hegde, D. Triyoso, 2007 .

Impact of Zr addition on properties of atomic layer deposited HfO2

B. E. White, Rama I. Hegde, Dina H. Triyoso, 2006 .

Physical and electrical properties of metal gate electrodes on HfO2 gate dielectrics

Bich-Yen Nguyen, Raghaw Rai, M. Zavala, 2003 .

Fermi-level pinning at the polysilicon/metal-oxide interface-Part II

M. L. Lovejoy, W.J. Taylor, J.M. Grant, 2004, IEEE Transactions on Electron Devices.

Tantalum carbonitride electrodes and the impact of interface chemistry on device characteristics

D. Gilmer, S. Samavedam, J. Schaeffer, 2007 .

A 7nm CMOS technology platform for mobile and high performance compute application

J. Zeng, S. Samavedam, B. Senapati, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Challenges for the integration of metal gate electrodes

S. Samavedam, E. Luckowski, C. Capasso, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Scaling of Hafnium-based High-k Dielectrics

D. Gilmer, S. Samavedam, J. Schaeffer, 2007 .

Electrical and materials properties of AlN/ HfO2 high-k stack with a metal gate

D. Gilmer, S. Samavedam, C. Gondran, 2009 .

Future Logic Scaling: Towards Atomic Channels and Deconstructed Chips

E. Beyne, N. Horiguchi, I. Radu, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

Interfacial defect states in HfO/sub 2/ and ZrO/sub 2/ nMOS capacitors

J.C. Lee, S. Mudanai, R. Nieh, 2002, IEEE Electron Device Letters.

Challenges for PMOS Metal Gate Electrodes and Solutions for Low Power Applications

D. Gilmer, S. Samavedam, A. Haggag, 2007 .

Characteristics of atomic-layer-deposited thin HfxZr1−xO2 gate dielectrics

Raghaw Rai, J. Schaeffer, Vidya Kaushik, 2007 .

Influence of stress induced CT local layout effect (LLE) on 14nm FinFET

Haojun Zhang, Xiaoli He, Manoj Joshi, 2017, 2017 Symposium on VLSI Technology.

Metal gates for advanced sub-80-nm SOI CMOS technology

S. Samavedam, J. Mogab, Philip J. Tobin, 2001, 2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207).

Effective work-function control technique applicable to p-type FinFET high-k/metal gate devices

Dongil Choi, Purushothaman Srinivasan, Xiaoli He, 2017, Microelectron. Reliab..

Analog, RF, and ESD device challenges and solutions for 14nm FinFET technology and beyond

Anil Kumar, Jagar Singh, Eller Manfred, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Fermi-level pinning at the polysilicon/metal oxide interface-Part I

M. L. Lovejoy, W.J. Taylor, J.M. Grant, 2004, IEEE Transactions on Electron Devices.

Fermi level pinning with sub-monolayer MeOx and metal gates [MOSFETs]

D. Gilmer, S. Samavedam, A. Demkov, 2003, IEEE International Electron Devices Meeting 2003.

Application of group electronegativity concepts to the effective work functions of metal gate electrodes on high- κ gate oxides

D. Gilmer, S. Samavedam, J. Schaeffer, 2007 .

Defect Structures in GaP/Si

S. Samavedam, B. Wessels, J. Woodall, 1995 .

Fully depleted SOI devices with TiN gate and elevated source-drain structures

J. Chen, S. Samavedam, L. Prabhu, 2000, 2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125).

NFET effective work function improvement via stress memorization technique in replacement metal gate technology

Y. Liu, S. Jain, S. Samavedam, 2013, 2013 Symposium on VLSI Technology.

Process and local layout effect interaction on a high performance planar 20nm CMOS

S. Samavedam, M. Sherony, X. Wu, 2013, 2013 Symposium on VLSI Technology.