David Biancolin

The Rocket Chip Generator

Adam M. Izraelevitz, Huy D. Vo, Albert J. Ou, 2016 .

Evaluation of RISC-V RTL with FPGA-Accelerated Simulation

K. Asanović, J. Bachrach, David Biancolin, 2017 .

Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs

Krste Asanovic, Daniel Grubb, Colin Schmidt, 2020, IEEE Micro.

FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud

Aditya Chopra, Jonathan Bachrach, Borivoje Nikolic, 2018, 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA).

Using FireSim to Enable Agile End-to-End RISC-V Computer Architecture Research

Albert J. Ou, K. Asanović, R. Katz, 2019 .

A Hardware Accelerator for Computing an Exact Dot Product

Krste Asanovic, Jonathan Bachrach, Jack Koenig, 2017, 2017 IEEE 24th Symposium on Computer Arithmetic (ARITH).

FASED: FPGA-Accelerated Simulation and Evaluation of DRAM

Krste Asanovic, Donggyu Kim, Jonathan Bachrach, 2019, FPGA.

FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud

K. Asanović, R. Katz, J. Bachrach, 2018, 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA).

Golden Gate: Bridging The Resource-Efficiency Gap Between ASICs and FPGA Prototypes

Jonathan Bachrach, Krste Asanović, David Biancolin, 2019, 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Simulator Independent Coverage for RTL Hardware Languages

J. Bachrach, Koushik Sen, B. Nikolić, 2023, ASPLOS.