B. Previtali

发表

3D sequential integration opportunities and technology optimization

F. Clermidy, C. Fenouillet-Béranger, P. Batude, 2014, IEEE International Interconnect Technology Conference.

3DVLSI with CoolCube process: An alternative path to scaling

O. Faynot, F. Clermidy, G. Ghibaudo, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

Impact of SOI, Si1-xGexOI and GeOI substrates on CMOS compatible Tunnel FET performance

F. Andrieu, S. Deleonibus, B. Previtali, 2008, 2008 IEEE International Electron Devices Meeting.

Advances in 3D CMOS sequential integration

A. Toffoli, O. Cueto, O. Faynot, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

First demonstration of ultrathin body c-SiGe channel FDSOI pMOSFETs combined with SiGe(:B) RSD: Drastic improvement of electrostatics (Vth,p tuning, DIBL) and transport (μ0, Isat) properties down to 23nm gate length

O. Faynot, J. Hartmann, O. Weber, 2011, 2011 International Electron Devices Meeting.

Enabling 3D Monolithic Integration

H. Grampeix, S. Deleonibus, P. Batude, 2008 .

3D monolithic integration: Technological challenges and electrical results

H. Grampeix, O. Faynot, S. Deleonibus, 2011 .

First demonstration of strained SiGe nanowires TFETs with ION beyond 700µA/µm

L. Selmi, J. Hartmann, L. Tosti, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

GeOI pMOSFETs Scaled Down to 30-nm Gate Length With Record Off-State Current

O. Faynot, M. Vinet, C. Tabone, 2010, IEEE Electron Device Letters.

Experimental evaluation of gate architecture influence on DG SOI MOSFETs performance

M. Vinet, S. Deleonibus, J. Widiez, 2005, IEEE Transactions on Electron Devices.

Ns laser annealing for junction activation preserving inter-tier interconnections stability within a 3D sequential integration

J. Hartmann, C. Fenouillet-Béranger, V. Lapras, 2016, 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Key process steps for high performance and reliable 3D Sequential Integration

C-M. V. Lu, A. Toffoli, T. Skotnicki, 2017, 2017 Symposium on VLSI Technology.

Full CMP integration of CVD TiN damascene sub-0.1-/spl mu/m metal gate devices for ULSI applications

S. Deleonibus, B. Previtali, M. Nier, 2001 .

Highly performant FDSOI pMOSFETs with metallic source/drain

O. Cueto, V. Balan, O. Faynot, 2009, 2009 International Symposium on VLSI Technology, Systems, and Applications.

FDSOI devices: A solution to achieve low junction leakage with low temperature processes (≤ 650°C)

O. Faynot, P. Batude, S. Cristoloveanu, 2012, 2012 13th International Conference on Ultimate Integration on Silicon (ULIS).

Ion-Ioff performance analysis of FDSOI MOSFETs with low processing temperature

M. Mouis, P. Batude, B. Previtali, 2010 .

Experimental Evidence of Sidewall Enhanced Transport Properties of Mesa-Isolated (001) Germanium-On-Insulator pMOSFETs

H. Grampeix, J. Hartmann, F. Allain, 2009, IEEE Transactions on Electron Devices.

300 K operating full-CMOS integrated Single Electron Transistor (SET)-FET circuits

B. De Salvo, O. Faynot, P. Perreau, 2012, 2012 International Electron Devices Meeting.

Low noise silicon CMOS single-electron transistors and electron pumps

G. Molas, S. Deleonibus, B. Previtali, 2008, 2008 Conference on Precision Electromagnetic Measurements Digest.

A tunable, dual mode field-effect or single electron transistor

B. Previtali, M. Vinet, V. Deshpande, 2012, 1201.3760.

(Invited) Cyclic Deposition/Etch Processes for the Formation of Si Raised Sources and Drains in Advanced MOSFETs

N. Cherkashin, J. Hartmann, B. Previtali, 2010 .

Size scaling of the addition spectra in silicon quantum dots

B. Previtali, M. Vinet, D. Mariolle, 2004, cond-mat/0411236.

Advanced characterizations of fluorine-free tungsten film and its application as low resistance liner for PCRAM

B. Previtali, F. Nemouchi, P. Rodriguez, 2017 .

Confined selective lateral epitaxial growth of 16-nm thick Ge nanostructures on SOI substrates: Advantages and challenges

S. Maitrejean, V. Lapras, B. Previtali, 2018 .

Mass Production of Silicon MOS-SETs: Can We Live with Nano-Devices' Variability?

Romain Wacquez, D. Kern, Marc Sanquer, 2011, FET.

Towards the limits of conventional MOSFETs: case of sub 30 nm NMOS devices

G. Guegan, Marc Sanquer, S. Deleonibus, 2004 .

Opportunities and challenges brought by 3D-sequential integration

G. Sicard, C. Fenouillet-Béranger, F. Andrieu, 2021, 2021 IEEE International Interconnect Technology Conference (IITC).

FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration

Maud Vinet, Mikaël Casse, Laurent Brunet, 2014, 2014 44th European Solid State Device Research Conference (ESSDERC).

Resist coating optimization on 8-in. deep-UV litho cell: modeling and application to 0.25-μm technology

Daniel Boutin, Andrew A. Blash, Jean Pierre Caire, 1995, Advanced Lithography.

Top-down fabrication and electrical characterization of Si and SiGe nanowires for advanced CMOS technologies

M. Cassé, V. Lapras, B. Previtali, 2019, Semiconductor Science and Technology.

A benchmark of co-flow and cyclic deposition/etch approaches for the selective epitaxial growth of tensile-strained Si:P

J. Hartmann, B. Previtali, M. Veillerot, 2017 .

Guidelines for intermediate back end of line (BEOL) for 3D sequential integration

Maud Vinet, M.-P. Samson, Charles-Antoine Guérin, 2017, 2017 47th European Solid-State Device Research Conference (ESSDERC).

3D Sequential Integration: Application-driven technological achievements and guidelines

X. Garros, O. Rozeau, O. Faynot, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Improved extraction of GIDL in FDSOI devices for proper junction quality analysis

M. Mouis, X. Garros, P. Batude, 2011, 2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC).

Dual metallic source and drain integration on planar Single and Double Gate SOI CMOS down to 20nm: Performance and scalability assessment

O. Faynot, M. Vinet, D. Lafond, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Advances, challenges and opportunities in 3D CMOS sequential integration

J. Mazurier, O. Faynot, P. Batude, 2011, 2011 International Electron Devices Meeting.

Performance and design considerations for gate-all-around stacked-NanoWires FETs

O. Rozeau, M. Vinet, F. Andrieu, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Strained tunnel FETs with record ION: first demonstration of ETSOI TFETs with SiGe channel and RSD

O. Faynot, F. Andrieu, O. Weber, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Patterning Strategy for Monoelectronic Device Platform in a Complementary Metal Oxide Semiconductor Technology

B. Previtali, M. Vinet, C. Vizioz, 2011 .

Experimental gate misalignment analysis on double gate SOI MOSFETs

M. Vinet, S. Deleonibus, J. Widiez, 2004, 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).

Sub-100nm high-K metal gate GeOI pMOSFETs performance: Impact of the Ge channel orientation and of the source injection velocity

M. Vinet, J.-M. Hartmann, E. Augendre, 2009, 2009 International Symposium on VLSI Technology, Systems, and Applications.

Low temperature boron and phosphorous doped SiGe for recessed and raised sources and drains

J. Hartmann, P. Batude, B. Previtali, 2011 .

7-Levels-Stacked Nanosheet GAA Transistors for High Performance Computing

F. Andrieu, B. Previtali, S. Barraud, 2020, 2020 IEEE Symposium on VLSI Technology.

Scaling of Trigate nanowire (NW) MOSFETs to sub-7 nm width: 300 K transition to Single Electron Transistor

O. Faynot, P. Perreau, L. Tosti, 2013 .

Scaling of Trigate nanowire (NW) MOSFETs Down to 5 nm Width: 300 K transition to Single Electron Transistor, challenges and opportunities

Romain Wacquez, Maud Vinet, Marc Sanquer, 2012, 2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC).

A new Si:C epitaxial channel nMOSFET architecture with improved drivability and short-channel characteristics

T. Ernst, J.-M. Hartmann, S. Deleonibus, 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

Investigation of bias-dependent series resistances and barrier height in Double Gate Schottky MOSFETs

J. Sallese, S. Deleonibus, B. Previtali, 2009, 2009 IEEE International SOI Conference.

Bonded planar double-metal-gate NMOS transistors down to 10 nm

M. Vinet, D. Lafond, S. Deleonibus, 2005, IEEE Electron Device Letters.

Monolithic 3D integration: A powerful alternative to classical 2D scaling

O. Rozeau, O. Faynot, G. Cibrario, 2014, 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Multigate silicon MOSFETs for 45 nm node and beyond

O. Faynot, Maud Vinet, S. Deleonibus, 2006 .

Self-Aligned Planar Double-Gate MOSFETs by Bonding for 22-nm Node, With Metal Gates, High- $\kappa$ Dielectrics, and Metallic Source/Drain

M. Vinet, D. Lafond, S. Deleonibus, 2009, IEEE Electron Device Letters.

Experimental comparison between double gate, ground plane, and single gate SOI CMOSFETs

S. Deleonibus, J. Widiez, B. Previtali, 2004, Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850).

First demonstration of a CMOS over CMOS 3D VLSI CoolCube™ integration on 300mm wafers

O. Faynot, P. Batude, M. Vinet, 2016, 2016 IEEE Symposium on VLSI Technology.

Multiple gate devices: advantages and challenges

O. Faynot, M. Vinet, S. Deleonibus, 2005 .

Opportunities brought by sequential 3D CoolCube™ integration

Gerald Cibrario, Olivier Billoint, Fabien Clermidy, 2016, 2016 46th European Solid-State Device Research Conference (ESSDERC).

GeOI and SOI 3D monolithic cell integrations for high density applications

X. Garros, O. Rozeau, O. Faynot, 2006, 2009 Symposium on VLSI Technology.

New insights on bottom layer thermal stability and laser annealing promises for high performance 3D VLSI

X. Garros, P. Batude, M. Vinet, 2014, 2014 IEEE International Electron Devices Meeting.

Single dopant impact on electrical characteristics of SOI NMOSFETs with effective length down to 10nm

O. Faynot, M. Vinet, B. Previtali, 2010, 2010 Symposium on VLSI Technology.