C. Tabone

发表

3D sequential integration opportunities and technology optimization

F. Clermidy, C. Fenouillet-Béranger, P. Batude, 2014, IEEE International Interconnect Technology Conference.

3DVLSI with CoolCube process: An alternative path to scaling

O. Faynot, F. Clermidy, G. Ghibaudo, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

Impact of SOI, Si1-xGexOI and GeOI substrates on CMOS compatible Tunnel FET performance

F. Andrieu, S. Deleonibus, B. Previtali, 2008, 2008 IEEE International Electron Devices Meeting.

Advances in 3D CMOS sequential integration

A. Toffoli, O. Cueto, O. Faynot, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

First demonstration of ultrathin body c-SiGe channel FDSOI pMOSFETs combined with SiGe(:B) RSD: Drastic improvement of electrostatics (Vth,p tuning, DIBL) and transport (μ0, Isat) properties down to 23nm gate length

O. Faynot, J. Hartmann, O. Weber, 2011, 2011 International Electron Devices Meeting.

Localized ultra-thin GeOI: An innovative approach to germanium channel MOSFETs on bulk Si substrates

G. Ghibaudo, T. Skotnicki, S. Monfray, 2008, 2008 IEEE International Electron Devices Meeting.

Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond

A. Toffoli, J. Cluzel, O. Faynot, 2010, 2010 Symposium on VLSI Technology.

Planar Fully depleted SOI technology: A powerful architecture for the 20nm node and beyond

O. Weber, C. Fenouillet-Béranger, P. Perreau, 2010, 2010 International Electron Devices Meeting.

Strained Si and Ge MOSFETs with high-k/metal gate stack for high mobility dual channel CMOS

N. Cherkashin, J. Hartmann, O. Weber, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Scaling of high-κ/metal-gate TriGate SOI nanowire transistors down to 10 nm width

Stephane Monfray, Frederic Boeuf, M.-P. Samson, 2013 .

Enabling 3D Monolithic Integration

H. Grampeix, S. Deleonibus, P. Batude, 2008 .

3D monolithic integration: Technological challenges and electrical results

H. Grampeix, O. Faynot, S. Deleonibus, 2011 .

Co-integration of 2 mV/dec Subthreshold Slope Impact Ionization MOS (I-MOS) with CMOS

S. Deleonibus, C. Tabone, F. Mayer, 2006, 2006 European Solid-State Device Research Conference.

First demonstration of strained SiGe nanowires TFETs with ION beyond 700µA/µm

L. Selmi, J. Hartmann, L. Tosti, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Detecting Unintended Schottky Junctions and Their Impact on Tunnel FET Characteristics

J. Hartmann, C. Tabone, M. Vinet, 2016, IEEE Transactions on Electron Devices.

High-$\kappa$ and Metal-Gate pMOSFETs on GeOI Obtained by Ge Enrichment: Analysis of ON and OFF Performances

R. Truche, Y. Campidelli, D. Bensahel, 2008, IEEE Electron Device Letters.

GeOI pMOSFETs Scaled Down to 30-nm Gate Length With Record Off-State Current

O. Faynot, M. Vinet, C. Tabone, 2010, IEEE Electron Device Letters.

Key process steps for high performance and reliable 3D Sequential Integration

C-M. V. Lu, A. Toffoli, T. Skotnicki, 2017, 2017 Symposium on VLSI Technology.

Strained Silicon Directly on Insulator N- and P-FET nanowire transistors

M. Cassé, F. Allain, C. Tabone, 2014, 2014 15th International Conference on Ultimate Integration on Silicon (ULIS).

Strain-induced performance enhancement of tri-gate and omega-gate nanowire FETs scaled down to 10nm Width

G. Reimbold, O. Faynot, G. Ghibaudo, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Scaling of Ω-gate SOI nanowire N- and P-FET down to 10nm gate length: Size- and orientation-dependent strain effects

O. Faynot, G. Ghibaudo, F. Allain, 2013, 2013 Symposium on VLSI Technology.

20nm gate length trigate pFETs on strained SGOI for high performance CMOS

X. Garros, O. Faynot, P. Batude, 2010, 2010 Symposium on VLSI Technology.

High-Performance Tunnel FETs on Advanced FDSOI Platform

J. Hartmann, M. Cassé, C. Tabone, 2014 .

Efficiency of mechanical stressors in Planar FDSOI n and p MOSFETs down to 14nm gate length

J. Mazurier, O. Faynot, G. Ghibaudo, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Copper-SilK integration in a 0.18 /spl mu/m double level metal interconnect

Yves Morand, Christian Arvet, T. Mourier, 1999, Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247).

FDSOI devices: A solution to achieve low junction leakage with low temperature processes (≤ 650°C)

O. Faynot, P. Batude, S. Cristoloveanu, 2012, 2012 13th International Conference on Ultimate Integration on Silicon (ULIS).

Characterization and simulation of STI isolation for 0.1 /spl mu/m partially-depleted SOI devices

O. Faynot, J. Pelloie, C. Fenouillet-Béranger, 2001, 2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207).

Experimental Evidence of Sidewall Enhanced Transport Properties of Mesa-Isolated (001) Germanium-On-Insulator pMOSFETs

H. Grampeix, J. Hartmann, F. Allain, 2009, IEEE Transactions on Electron Devices.

Comparison between <100> and <110> oriented channels in highly strained FDSOI pMOSFETs

A. Toffoli, O. Faynot, G. Ghibaudo, 2012, 2012 IEEE International SOI Conference (SOI).

Optimizing the salicide thickness for improving 130 nm PD SOI performances

S. Haendler, R. Gwoziecki, C. Tabone, 2003, 2003 IEEE International Conference on SOI.

High mobility CMOS: First demonstration of planar GeOI p-FETs with SOI n-FETs

H. Grampeix, J. Hartmann, P. Batude, 2011 .

Investigations of the ionizing radiation induced effects in ultra-thin strained-silicon layers on insulator using confocal microscopy measurements

O. Faynot, F. Andrieu, C. Tabone, 2011 .

Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain

O. Rozeau, O. Faynot, M. Vinet, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Opportunities and challenges brought by 3D-sequential integration

G. Sicard, C. Fenouillet-Béranger, F. Andrieu, 2021, 2021 IEEE International Interconnect Technology Conference (IITC).

Schottky Barrier Height Extraction in Ohmic Regime: Contacts on Fully Processed GeOI Substrates

C. Tabone, M. Vinet, L. Hutin, 2009 .

Improved extraction of GIDL in FDSOI devices for proper junction quality analysis

M. Mouis, X. Garros, P. Batude, 2011, 2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC).

Tunneling field-effect transistor with epitaxial junction in thin germanium-on-insulator

Sorin Cristoloveanu, Laurent Clavelier, Dimitrios Kazazis, 2009 .

Advances, challenges and opportunities in 3D CMOS sequential integration

J. Mazurier, O. Faynot, P. Batude, 2011, 2011 International Electron Devices Meeting.

Strained tunnel FETs with record ION: first demonstration of ETSOI TFETs with SiGe channel and RSD

O. Faynot, F. Andrieu, O. Weber, 2012, 2012 Symposium on VLSI Technology (VLSIT).

High performance 70 nm gate length germanium-on-insulator pMOSFET with high-k/metal gate

X. Garros, G. Reimbold, Emmanuel Augendre, 2009 .

105 nm Gate length pMOSFETs with high-K and metal gate fabricated in a Si process line on 200 mm GeOI wafers

G. Le Carval, M. Vinet, S. Deleonibus, 2008 .

Sub-100nm high-K metal gate GeOI pMOSFETs performance: Impact of the Ge channel orientation and of the source injection velocity

M. Vinet, J.-M. Hartmann, E. Augendre, 2009, 2009 International Symposium on VLSI Technology, Systems, and Applications.

Double SiGe:C diffusion barrier channel 40nm CMOS with improved short-channel performances

A. Toffoli, J. Cluzel, J. Hartmann, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate silicon nanowire MOSFETs

G. Reimbold, Hiroshi Iwai, Gerard Ghibaudo, 2013 .

Scaling of high-k/metal-gate Trigate SOI nanowire transistors down to 10nm width

G. Ghibaudo, P. Leroux, C. Tabone, 2012, 2012 13th International Conference on Ultimate Integration on Silicon (ULIS).

Monolithic 3D integration: A powerful alternative to classical 2D scaling

O. Rozeau, O. Faynot, G. Cibrario, 2014, 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

High performance low temperature activated devices and optimization guidelines for 3D VLSI integration of FD, TriGate, FinFET on insulator

O. Rozeau, G. Ghibaudo, P. Batude, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

First demonstration of a CMOS over CMOS 3D VLSI CoolCube™ integration on 300mm wafers

O. Faynot, P. Batude, M. Vinet, 2016, 2016 IEEE Symposium on VLSI Technology.

NSP: Physical compact model for stacked-planar and vertical Gate-All-Around MOSFETs

O. Rozeau, O. Faynot, M. Vinet, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

GeOI and SOI 3D monolithic cell integrations for high density applications

X. Garros, O. Rozeau, O. Faynot, 2006, 2009 Symposium on VLSI Technology.