Wei Lin

Prototype of multi-stacked memory wafers using low-temperature oxide bonding and ultra-fine-dimension copper through-silicon via interconnects

T. Graves-abe, K. Winstel, D. Berger, 2014, 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology

T. Graves-abe, C. Kothandaraman, B. Himmel, 2014 .

Low-Temperature Oxide Wafer Bonding for 3-D Integration: Chemistry of Bulk Oxide Matters

Wei Lin, S. Skordas, A. Madan, 2014, IEEE Transactions on Semiconductor Manufacturing.

Study Photo Imagable dielectric (PID) and non-PID on process, fabrication and reliability by using panel glass substrate for next generation interconnection

Wei Lin, Po-Chiang Wang, C. Chien, 2019, International Symposium on Microelectronics.

Wafer-scale oxide fusion bonding and wafer thinning development for 3D systems integration: Oxide fusion wafer bonding and wafer thinning development for TSV-last integration

R. Hannon, S. Kanakasabapathy, A. Upham, 2012, 2012 3rd IEEE International Workshop on Low Temperature Bonding for 3D Integration.

Three-dimensional wafer stacking using Cu TSV integrated with 45nm high performance SOI-CMOS embedded DRAM technology

Toshiaki Kirihata, John Golz, Alex Hubbard, 2013, 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).