D. Canaperi

发表

Prototype of multi-stacked memory wafers using low-temperature oxide bonding and ultra-fine-dimension copper through-silicon via interconnects

T. Graves-abe, K. Winstel, D. Berger, 2014, 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Effects of overlayers on electromigration reliability improvement for Cu/low K interconnects

D. Restaino, A. Simon, M. Krishnan, 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

Electromigration extendibility of Cu(Mn) alloy-seed interconnects, and understanding the fundamentals

A. Simon, D. Edelstein, A. Uedono, 2012, 2012 International Electron Devices Meeting.

Fabrication and mobility characteristics of ultra-thin strained Si directly on insulator (SSDOI) MOSFETs

M. Ieong, L. Shi, D. Boyd, 2003, IEEE International Electron Devices Meeting 2003.

Silicon Carrier with Deep Through-Vias, Fine Pitch Wiring and Through Cavity for Parallel Optical Transceiver

D. Edelstein, P. Andry, C. Tsang, 2005, Proceedings Electronic Components and Technology, 2005. ECTC '05..

Novel low k Dielectric materials for nano device interconnect technology

T. Standaert, B. Peethala, D. Canaperi, 2020, 2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

SiGe-on-insulator prepared by wafer bonding and layer transfer for high-performance field-effect transistors

H.-S. Philip Wong, Steven J. Koester, Jack O. Chu, 2001 .

Extreme-low k porous pSiCOH dielectrics prepared by PECVD

Stephan A. Cohen, A. Grill, Matthew Shoudy, 2018 .

CMP Defect Reduction and Mitigation: Practices and Future Trends

D. Canaperi, W. Tseng, C. Silvestre, 2021, 2021 32nd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).

Post porosity plasma protection integration at 48 nm pitch

T. Standaert, D. Edelstein, A. Grill, 2016, 2016 IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC).

Processing and moisture effects on TDDB for Cu/ULK BEOL structures

Stephan A. Cohen, S. Gates, D. Canaperi, 2012 .

Effects of chemical mechanical polishing on a porous SiCOH dielectric

Stephan A. Cohen, S. Gates, M. Krishnan, 2012 .

Ultrathin conformal multilayer SiNO dielectric cap for capacitance reduction in Cu/low k interconnects

D. Edelstein, A. Grill, D. Priyadarshini, 2016, 2016 IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC).

Pinch Off Plasma CVD Deposition Process and Material Technology for Nano-Device Air Gap/Spacer Formation

D. Canaperi, Chanro Park, K. Cheng, 2018 .

Advanced metal and dielectric barrier cap films for Cu low k interconnects

A. Simon, D. Edelstein, A. Grill, 2014, IEEE International Interconnect Technology Conference.

High reliability 32 nm Cu/ULK BEOL based on PVD CuMn seed, and its extendibility

A. Simon, D. Edelstein, C. Cabral, 2010, 2010 International Electron Devices Meeting.

Ultrathin (8-14 nm) Conformal SiN for sub-20 nm Copper/Low-k Interconnects

Daniel C. Edelstein, Alfred Grill, Jay Burnham, 2014 .

Atom motion of Cu and Co in Cu damascene lines with a CoWP cap

Robert Rosenberg, S. T. Chen, C-K. Hu, 2004 .

High-performance SiGe MODFET technology

S. Koester, J. Ott, D. Canaperi, 2004 .

BEOL Cu CMP Process Evaluation for Advanced Technology Nodes

Christopher J. Waskiewicz, Christopher J. Penny, R. Patlolla, 2013 .

Reducing Time Dependent Line to Line Leakage Following Post CMP Clean

Satyavolu S. Papa Rao, D. Canaperi, M. Smalley, 2010 .

CMP Challenges for Advanced Technology Nodes

R. Patlolla, J. Wynne, D. Canaperi, 2017 .

Ruthenium interconnect resistivity and reliability at 48 nm pitch

Wei Wang, Raghuveer Patlolla, Huai Huang, 2016, 2016 IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC).

Electromigration Cu mass flow in Cu interconnections

Robert Rosenberg, Andrew H. Simon, S. T. Chen, 2006 .

Laterally scaled Si-Si/sub 0.7/Ge/sub 0.3/ n-MODFETs with f/sub max/>200 GHz and low operating bias

S. Koester, K. Jenkins, J. Ott, 2005, IEEE Electron Device Letters.

Experimental study of nanoscale Co damascene BEOL interconnect structures

D. Edelstein, J. Kelly, B. Peethala, 2016, 2016 IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC).

Post Cu CMP cleaning process evaluation for 32nm and 22nm technology nodes

L. Economikos, Jianping Zheng, J. Muncy, 2012, 2012 SEMI Advanced Semiconductor Manufacturing Conference.

Improved DC and RF performance in Si/SiGe n-MODFETs with ion-implanted buried p-well doping

S. Koester, J. Ott, D. Canaperi, 2005, IEEE Electron Device Letters.

Thermal Stability of Copper Contact Metallization Using Ru-Containing Liner

C. Hu, B. Haran, D. Canaperi, 2011 .

First Experimental Demonstration of MRAM Data Scrubbing: 80 Mb MRAM with 40 nm junctions for Last Level Cache Applications

D. Edelstein, R. Johnson, J. Slaughter, 2021, International Electron Devices Meeting.

Impact of surface preparation for n-type Si

B. Peethala, D. Canaperi, M. Raymond, 2017 .

A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

B. Lherron, D. Chanemougame, P. Oldiges, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

CVD Co and its application to Cu damascene interconnections

A. Simon, D. Edelstein, C. Cabral, 2010, 2010 IEEE International Interconnect Technology Conference.

A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

P. Oldiges, C. Park, N. Loubet, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Electron and hole mobility enhancement in strained SOI by wafer bonding

James L. Speidell, Steven A. Cordes, Steven J. Koester, 2002 .

80 nm gate-length Si/Si0.7Ge0.3 n-MODFET with 194 GHz fmax

Christopher V. Jahnes, John A. Ott, Michael J. Rooks, 2003 .

The Effect of Material and Process Interactions on BEOL Integration

John C. Arnold, Terry A. Spooner, Satyavolu S. Papa Rao, 2009 .

CMP Development for Ru Liner Structures beyond 14nm

T. Standaert, B. Peethala, R. Patlolla, 2018 .

A novel ALD SiBCN low-k spacer for parasitic capacitance reduction in FinFETs

S. Narasimha, J. Johnson, M. Khare, 2015, Symposium on VLSI Technology.

Study of field-driven wall-configuration conversions for laminated Permalloy in the easy-axis state

D. Canaperi, P. Trouilloud, S. Krongelb, 1988 .

Edge-curling-wall discontinuities and interactions with Bloch walls in easy-axis Permalloy

D. Canaperi, P. Trouilloud, L. Romankiw, 1988 .

CMP Challenges for Advanced Technology Nodes beyond Si

R. Patlolla, D. Canaperi, W. Kleemeier, 2017 .