S. Verhaegen

Freeform illumination sources: an experimental study of source-mask optimization for 22-nm SRAM cells

G. Vandenberghe, J. Finders, S. Verhaegen, 2010, Advanced Lithography.

Challenges in patterning 45nm node multiple-gate devices and SRAM cells

Vincent Wiaux, Rita Rooyackers, Staf Verhaegen, 2004 .

Litho variations and their impact on the electrical yield of a 32nm node 6TSRAM cell design for manufacturability through design-proces integration II

Geert Vandenberghe, Wim Dehaene, Staf Verhaegen, 2008 .

Integration of tall triple-gate devices with inserted TaxNy gate in a 0.274µm2 6T-SRAM cell and advanced CMOS logic circuits

Vincent Wiaux, Geert Vandenberghe, Patrick Jaenen, 2005 .

Double-patterning interactions with wafer processing, optical proximity correction, and physical design flows

Vincent Wiaux, Staf Verhaegen, Kevin Lucas, 2009 .

Double patterning design split implementation and validation for the 32nm node

Vincent Wiaux, Eric Hendrickx, Staf Verhaegen, 2007, SPIE Advanced Lithography.

A 0.314/spl mu/m/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm applications using 0.75NA 193nm lithography

R. Rooyackers, M. Van Hove, K. Ronse, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

High yield sub-0.1µm2 6T-SRAM cells, featuring high-k/metal-gate finfet devices, double gate patterning, a novel fin etch strategy, full-field EUV lithography and optimized junction design & layout

K. Ronse, S. Locorotondo, V. Truffert, 2010, 2010 Symposium on VLSI Technology.

Challenges in using optical lithography for the building of a 22nm node 6T-SRAM cell

Naoto Horiguchi, Anabela Veloso, S. Locorotondo, 2010 .

Demonstration of scaled 0.099µm2 FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technology

R. Rajagopalan, K. Ronse, S. Locorotondo, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).