A. Pleszkun

发表

A modified approach to data cache management

Gary S. Tyson, Andrew R. Pleszkun, Matthew Farrens, 1995, MICRO 1995.

MISC: a Multiple Instruction Stream Computer

Gary S. Tyson, Andrew R. Pleszkun, Matthew K. Farrens, 1992, MICRO 25.

Pipe: a high performance VLSI architecture

Randy H. Katz, Andrew R. Pleszkun, James E. Smith, 1983 .

The performance potential of multiple functional unit processors

G. Sohi, A. Pleszkun, 1988, [1988] The 15th Annual International Symposium on Computer Architecture. Conference Proceedings.

PIPE: a VLSI decoupled architecture

Andrew R. Pleszkun, James R. Goodman, Jian-tu Hsieh, 1985, ISCA '85.

d d OVERVIEW OF THE PIPE PROCESSOR IMPLEMENTATION

M. Farrens, A. Pleszkun, 1991 .

Misc: A Multiple Instruction Stream Computer

G. Tyson, M. Farrens, A. Pleszkun, 1992, [1992] Proceedings the 25th Annual International Symposium on Microarchitecture MICRO 25.

Features of the Structured Memory Access (SMA) Architecture

Andrew R. Pleszkun, Gurindar S. Sohi, Edward S. Davidson, 1986, IEEE Computer Society International Conference.

Confidence estimation for speculation control

D. Grunwald, A. Klauser, D. Grunwald, 1998, Proceedings. 25th Annual International Symposium on Computer Architecture (Cat. No.98CB36235).

The Architecture of Lisp Machines

Andrew R. Pleszkun, Matthew J. Thazhuthaveetil, M. J. Thazhuthaveetil, 1987, Computer.

Strategies for Achieving

Andrew R. Pleszkun, Matthew Farrens, M. Farrens, 1991 .

The performance potential of multiple functional unit processors

Andrew R. Pleszkun, Gurindar S. Sohi, G. Sohi, 1988, [1988] The 15th Annual International Symposium on Computer Architecture. Conference Proceedings.

A performance analysis of the iSCSI protocol

Dirk Grunwald, Andrew R. Pleszkun, Stephen Aiken, 2003, 20th IEEE/11th NASA Goddard Conference on Mass Storage Systems and Technologies, 2003. (MSST 2003). Proceedings..

Multiple Instruction Issue And Single-chip Processors

G. Sohi, A. Pleszkun, 1988, [1988] Proceedings of the 21st Annual Workshop on Microprogramming and Microarchitecture - MICRO '21.

An Algorithm for Design Rule Checking on a Multiprocessor

Andrew R. Pleszkun, George E. Bier, A. Pleszkun, 1985, 22nd ACM/IEEE Design Automation Conference.

Implementation of precise interrupts in pipelined processors

Andrew R. Pleszkun, James E. Smith, James E. Smith, 1985, ISCA '98.

Managing data caches using selective cache line replacement

Gary S. Tyson, Andrew R. Pleszkun, John Matthews, 1997, International Journal of Parallel Programming.

A modified approach to data cache management

Gary S. Tyson, Andrew R. Pleszkun, John Matthews, 1995, Proceedings of the 28th Annual International Symposium on Microarchitecture.

Implementation of precise interrupts in pipelined processors

James E. Smith, A. Pleszkun, 1985, ISCA '85.

PIPE: a VLSI decoupled architecture

Andrew R. Pleszkun, James R. Goodman, Honesty C. Young, 1985, ISCA '85.

Implementing Precise Interrupts in Pipelined Processors

Andrew R. Pleszkun, James E. Smith, James E. Smith, 1988, IEEE Trans. Computers.

WISQ: a restartable architecture using queues

Andrew R. Pleszkun, Philip J. Woest, James R. Goodman, 1987, ISCA '87.

Proceedings of the 24th annual international symposium on Computer architecture

Trevor Mudge, Andrew R. Pleszkun, T. Mudge, 1997 .

A study of single-chip processor/cache organizations for large numbers of transistors

G. Tyson, M. Farrens, A. Pleszkun, 1994, Proceedings of 21 International Symposium on Computer Architecture.

Implementation of the PIPE processor

Andrew R. Pleszkun, Matthew K. Farrens, M. Farrens, 1991, Computer.