A. Agarwal

发表

A 320 mV 56 μW 411 GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65 nm CMOS

S. Borkar, R.K. Krishnamurthy, S.K. Mathew, 2009, IEEE Journal of Solid-State Circuits.

53 Gbps Native ${\rm GF}(2 ^{4}) ^{2}$ Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors

Sanu Mathew, Mark Anders, Himanshu Kaul, 2011, IEEE Journal of Solid-State Circuits.

A 300 mV 494GOPS/W Reconfigurable Dual-Supply 4-Way SIMD Vector Processing Accelerator in 45 nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2009, IEEE Journal of Solid-State Circuits.

μRNG: A 300–950mV 323Gbps/W all-digital full-entropy true random number generator in 14nm FinFET CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2015, ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC).

A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS

Himanshu Kaul, Amit Agarwal, Gregory K. Chen, 2021, IEEE Journal of Solid-State Circuits.

A 2.9–33.0 TOPS/W Reconfigurable 1-D/2-D Compute-Near-Memory Inference Accelerator in 10-nm FinFET CMOS

Himanshu Kaul, Amit Agarwal, Gregory K. Chen, 2020, IEEE Solid-State Circuits Letters.

2.9TOPS/W Reconfigurable Dense/Sparse Matrix-Multiply Accelerator with Unified INT8/INTI6/FP16 Datapath in 14NM Tri-Gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2018, 2018 IEEE Symposium on VLSI Circuits.

18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2010, 2010 Proceedings of ESSCIRC.

3GHz, 74mW 2-level Karatsuba 64b Galois field multiplier for public-key encryption acceleration in 45nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2010, 2010 Proceedings of ESSCIRC.

A 7-Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS

Vikram B. Suresh, S. Hsu, S. Mathew, 2023, IEEE Journal of Solid-State Circuits.

A 4900- $\mu$ m2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition

Sudhir Satpathy, Vikram Suresh, Himanshu Kaul, 2020, IEEE Journal of Solid-State Circuits.

A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS

Sanu Mathew, Sudhir Satpathy, Mark Anders, 2014, IEEE Journal of Solid-State Circuits.

An All-Digital Unified Static/Dynamic Entropy Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction for Secure Privacy-Preserving Mutual Authentication in IoT Mote Platforms

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2018, 2018 IEEE Symposium on VLSI Circuits.

2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors

Himanshu Kaul, Amit Agarwal, Ram Krishnamurthy, 2012, IEEE Journal of Solid-State Circuits.

A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS

Vikram Suresh, Himanshu Kaul, Amit Agarwal, 2019, IEEE Journal of Solid-State Circuits.

A 4fJ/bit delay-hardened physically unclonable function circuit with selective bit destabilization in 14nm tri-gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

$\mu $ RNG: A 300–950 mV, 323 Gbps/W All-Digital Full-Entropy True Random Number Generator in 14 nm FinFET CMOS

Vikram Suresh, Himanshu Kaul, Amit Agarwal, 2016, IEEE Journal of Solid-State Circuits.

13fJ/bit probing-resilient 250K PUF array with soft darkbit masking for 1.94% bit-error in 22nm tri-gate CMOS

Sanu Mathew, Sudhir Satpathy, Mark Anders, 2014, ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC).

16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS

Himanshu Kaul, Amit Agarwal, Gregory K. Chen, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

A 9.0-TOPS/W Hash-Based Deep Neural Network Accelerator Enabling 128× Model Compression in 10-nm FinFET CMOS

Himanshu Kaul, Amit Agarwal, Gregory K. Chen, 2020, IEEE Solid-State Circuits Letters.

On-Chip High-Resolution Timing Characterization Circuits for Memory IPs

S. Hsu, R. Krishnamurthy, J. Tschanz, 2022, European Solid-State Circuits Conference.

25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

A 32nm 8.3GHz 64-entry × 32b variation tolerant near-threshold voltage register file

Sanu Mathew, Mark Anders, Himanshu Kaul, 2010, 2010 Symposium on VLSI Circuits.

340 mV–1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2015, IEEE Journal of Solid-State Circuits.

53Gbps native GF(24)2 composite-field AES-encrypt/decrypt accelerator for content-protection in 45nm high-performance microprocessors

Sanu Mathew, Mark Anders, Himanshu Kaul, 2010, 2010 Symposium on VLSI Circuits.

A 230mV-950mV 2.8Tbps/W Unified SHA256/SM3 Secure Hashing Hardware Accelerator in 14nm Tri-Gate CMOS

Sanu Mathew, Sudhir Satpathy, Vikram Suresh, 2018, ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC).

A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS

Sanu Mathew, Mark Anders, Himanshu Kaul, 2012, 2012 IEEE International Solid-State Circuits Conference.