S. Pravossoudovitch

发表

Using TMR Architectures for Yield Improvement

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.

An optimized BIST test pattern generator for delay testing

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

Efficient scan chain design for power minimization during scan testing under routing constraint

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

Design of routing-constrained low power scan chains

P. Girard, C. Landrault, S. Pravossoudovitch, 2004 .

Analysis and Fault Modeling of Actual Resistive Defects in Flash Memories

Arnaud Virazel, Serge Pravossoudovitch, Alberto Bosio, 2011 .

Evaluating An SEU Monitor For Mixed-Field Radiation Environments

A. Bosio, P. Girard, S. Pravossoudovitch, 2013 .

A Robust Infrastructure for Data Collection and Transfer for a Distributed SRAM-based Neutron Detection Platform

A. Bosio, P. Girard, S. Pravossoudovitch, 2011 .

Mapping Test Power to Functional Power through Smart X-Filling for LOS Scheme

Xiaoqing Wen, Arnaud Virazel, Alberto Bosio, 2011 .

Scan Cell Reordering for Peak Power Reduction during Test Cycles

P. Girard, C. Landrault, S. Pravossoudovitch, 2006 .

Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes

A. Bosio, P. Girard, S. Pravossoudovitch, 2012, Journal of Electronic Testing.

Multiple Cell Upset Classification in Commercial SRAMs

G. Tsiligiannis, L. Dilillo, A. Bosio, 2014, IEEE Transactions on Nuclear Science.

Multiple-Cell-Upsets on a commercial 90nm SRAM in dynamic mode

G. Tsiligiannis, L. Dilillo, A. Bosio, 2013, 2013 14th European Conference on Radiation and Its Effects on Components and Systems (RADECS).

New March Elements for Address Decoder Open and Resistive Open Fault Detection in SRAM Memories

Arnaud Virazel, Luigi Dilillo, Simone Borri, 2008 .

ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2006, J. Electron. Test..

Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2005, J. Electron. Test..

Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2005, J. Electron. Test..

Efficient Test of Dynamic Read Destructive Faults in SRAM Memories

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2005 .

Resistive-open defects in embedded-SRAM core cells: analysis and march test solution

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2004, 13th Asian Test Symposium.

Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2004, Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004..

March iC-: an improved version of March C- for ADOFs detection

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

March Tests Improvements for Address Decoder Open and Resistive Open Fault Detection

Arnaud Virazel, Luigi Dilillo, Simone Borri, 2004 .

Comparison of open and resistive-open defect test conditions in SRAM address decoders

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2003, 2003 Test Symposium.

Defect-oriented dynamic fault models for embedded-SRAMs

S. Pravossoudovitch, A. Virazel, P. Girard, 2003, The Eighth IEEE European Test Workshop, 2003. Proceedings..

Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity

João Paulo Teixeira, Serge Pravossoudovitch, Christian Landrault, 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014, J. Electron. Test..

A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2011, 2011 Asian Test Symposium.

Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

A test solution for oxide thickness variations in the ATMEL TSTAC™ eFlash technology

L. Dilillo, A. Bosio, P. Girard, 2011, 2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

A new design-for-test technique for SRAM core-cell stability faults

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

A Design-for-Diagnosis Technique for SRAM Write Drivers

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2008, 2008 Design, Automation and Test in Europe.

RSIC Generation: A Solution for Logic BIST

Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault, 2008 .

Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2007, J. Electron. Test..

Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2007, 12th IEEE European Test Symposium (ETS'07).

Slow Write Driver Faults in 65nm SRAM Technology: Analysis and March Test Solution

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

Minimizing peak power consumption during scan testing: test pattern modification with X filling heuristics

P. Girard, A. Virazel, C. Landrault, 2006, International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006..

Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2006, 2006 IFIP International Conference on Very Large Scale Integration.

Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2005, PATMOS.

Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 /spl mu/m and 90nm technologies

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Data retention fault in SRAM memories: analysis and detection procedures

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2005, VLSI-SoC.

Parity prediction synthesis for nano-electronic gate designs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010, 2010 IEEE International Test Conference.

SoC Yield Improvement - Using TMR Architectures for Manufacturing Defect Tolerance in Logic Cores

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010 .

Yield Improvement, Fault-Tolerance to the Rescue?

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2008, 2008 14th IEEE International On-Line Testing Symposium.

Low power BIST design by hypergraph partitioning: methodology and architectures

Patrick Girard, Serge Pravossoudovitch, Christian Landrault, 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

Comparison between random and pseudo-random generation for BIST of delay, stuck-at and bridging faults

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2000, Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646).

A statistical simulation method for reliability analysis of SRAM core-cells

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010, Design Automation Conference.

Reliable method for delay-fault diagnosis

Serge Pravossoudovitch, Christian Landrault, Patrick Girard, 1991 .

Advanced Test Methods for SRAMs: Effective Solutions for Dynamic Fault Detection in Nanoscaled Technologies

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2009 .

High Defect Coverage with Low-Power Test Sequences in a BIST Environment

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2002, IEEE Des. Test Comput..

On using efficient test sequences for BIST

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

90 nm SRAM Static and Dynamic Mode Real-Time Testing at Concordia Station in Antarctica

G. Tsiligiannis, L. Dilillo, A. Bosio, 2014, IEEE Transactions on Nuclear Science.

High quality TPG for delay faults in look-up tables of FPGAs

Patrick Girard, Serge Pravossoudovitch, Michel Renovell, 2004, Proceedings. DELTA 2004. Second IEEE International Workshop on Electronic Design, Test and Applications.

Defect analysis for delay-fault BIST in FPGAs

Patrick Girard, Serge Pravossoudovitch, Michel Renovell, 2003, 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003..

An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs

Patrick Girard, Serge Pravossoudovitch, Michel Renovell, 2006, J. Electron. Test..

Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs

Patrick Girard, Serge Pravossoudovitch, Michel Renovell, 2005, J. Electron. Test..

A Memory Fault Simulator for Radiation-Induced Effects in SRAMs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010, 2010 19th IEEE Asian Test Symposium.

Evaluating a radiation monitor for mixed-field environments based on SRAM technology

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014 .