A. Virazel

发表

Using TMR Architectures for Yield Improvement

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.

A. Bosio, P. Girard, A. Virazel, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Design of routing-constrained low power scan chains

P. Girard, C. Landrault, S. Pravossoudovitch, 2004 .

Analysis and Fault Modeling of Actual Resistive Defects in Flash Memories

Arnaud Virazel, Serge Pravossoudovitch, Alberto Bosio, 2011 .

Power Conscious BIST Approaches

H. Wunderlich, A. Virazel, 2002 .

Evaluating An SEU Monitor For Mixed-Field Radiation Environments

A. Bosio, P. Girard, S. Pravossoudovitch, 2013 .

2015 JETTA Reviewers

Robert Wille, Yong-Bin Kim, Alexandre M. Amory, 2016, Journal of electronic testing.

Mapping Test Power to Functional Power through Smart X-Filling for LOS Scheme

Xiaoqing Wen, Arnaud Virazel, Alberto Bosio, 2011 .

An Effective Power-Aware At-Speed Test Methodology for IP Qualification and Characterization

Rajesh Kumar Immadi, P. Girard, A. Virazel, 2016, Journal of Electronic Testing.

A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems

H. Wunderlich, A. Bosio, P. Girard, 2014, Journal of Electronic Testing.

Scan Cell Reordering for Peak Power Reduction during Test Cycles

P. Girard, C. Landrault, S. Pravossoudovitch, 2006 .

Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes

A. Bosio, P. Girard, S. Pravossoudovitch, 2012, Journal of Electronic Testing.

Improving TID Radiation Robustness of a CMOS OxRAM-Based Neuron Circuit by Using Enclosed Layout Transistors

Arnaud Virazel, Patrick Girard, Hassen Aziza, 2021, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Survey of Test and Reliability Solutions for Magnetic Random Access Memories

Mehdi B. Tahoori, Rajendra Bishnoi, Patrick Girard, 2021, Proceedings of the IEEE.

TSV aware timing analysis and diagnosis in paths with multiple TSVs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014, 2014 IEEE 32nd VLSI Test Symposium (VTS).

Dynamic Test Methods for COTS SRAMs

G. Tsiligiannis, L. Dilillo, A. Bosio, 2014, IEEE Transactions on Nuclear Science.

Multiple Cell Upset Classification in Commercial SRAMs

G. Tsiligiannis, L. Dilillo, A. Bosio, 2014, IEEE Transactions on Nuclear Science.

Multiple-Cell-Upsets on a commercial 90nm SRAM in dynamic mode

G. Tsiligiannis, L. Dilillo, A. Bosio, 2013, 2013 14th European Conference on Radiation and Its Effects on Components and Systems (RADECS).

Testing a Commercial MRAM Under Neutron and Alpha Radiation in Dynamic Mode

G. Tsiligiannis, L. Dilillo, A. Bosio, 2013, IEEE Transactions on Nuclear Science.

Dynamic Mode Test of a Commercial 4Mb Toggle MRAM under Neutron Radiation

Arnaud Virazel, Patrick Girard, Alberto Bosio, 2012 .

Evaluation of test algorithms stress effect on SRAMs under neutron radiation

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2012, 2012 IEEE 18th International On-Line Testing Symposium (IOLTS).

SRAM testing under Neutron Radiation for the evaluation of different algorithms stress

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2012 .

New March Elements for Address Decoder Open and Resistive Open Fault Detection in SRAM Memories

Arnaud Virazel, Luigi Dilillo, Simone Borri, 2008 .

ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2006, J. Electron. Test..

Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2005, J. Electron. Test..

Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2005, J. Electron. Test..

Efficient Test of Dynamic Read Destructive Faults in SRAM Memories

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2005 .

Resistive-open defects in embedded-SRAM core cells: analysis and march test solution

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2004, 13th Asian Test Symposium.

Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2004, Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004..

March iC-: an improved version of March C- for ADOFs detection

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

March Tests Improvements for Address Decoder Open and Resistive Open Fault Detection

Arnaud Virazel, Luigi Dilillo, Simone Borri, 2004 .

Comparison of open and resistive-open defect test conditions in SRAM address decoders

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2003, 2003 Test Symposium.

Defect-oriented dynamic fault models for embedded-SRAMs

S. Pravossoudovitch, A. Virazel, P. Girard, 2003, The Eighth IEEE European Test Workshop, 2003. Proceedings..

An Experimental Comparative Study of Fault-Tolerant Architectures

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2015 .

An effective ATPG flow for Gate Delay Faults

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2015, 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014, J. Electron. Test..

Performance Characterization of TAS-MRAM Architectures in Presence of Capacitive Defects

Alberto Bosio, Luigi Dilillo, Patrick Girard, 2013 .

Test solution for data retention faults in low-power SRAMs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Impact of Resistive-Bridge Defects in TAS-MRAM Architectures

L. Dilillo, A. Bosio, A. Todri, 2012, 2012 IEEE 21st Asian Test Symposium.

Why and How Controlling Power Consumption during Test: A Survey

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2012, 2012 IEEE 21st Asian Test Symposium.

A pseudo-dynamic comparator for error detection in fault tolerant architectures

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2012, 2012 IEEE 30th VLSI Test Symposium (VTS).

Impact of resistive-open defects on the heat current of TAS-MRAM architectures

Luigi Dilillo, Aida Todri, Alberto Bosio, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2011, 2011 Asian Test Symposium.

Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

A test solution for oxide thickness variations in the ATMEL TSTAC™ eFlash technology

L. Dilillo, A. Bosio, P. Girard, 2011, 2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

A new design-for-test technique for SRAM core-cell stability faults

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

A Design-for-Diagnosis Technique for SRAM Write Drivers

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2008, 2008 Design, Automation and Test in Europe.

RSIC Generation: A Solution for Logic BIST

Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault, 2008 .

Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2007, J. Electron. Test..

Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2007, 12th IEEE European Test Symposium (ETS'07).

Slow Write Driver Faults in 65nm SRAM Technology: Analysis and March Test Solution

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

Minimizing peak power consumption during scan testing: test pattern modification with X filling heuristics

P. Girard, A. Virazel, C. Landrault, 2006, International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006..

Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2006, 2006 IFIP International Conference on Very Large Scale Integration.

Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2005, PATMOS.

Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 /spl mu/m and 90nm technologies

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Data retention fault in SRAM memories: analysis and detection procedures

Arnaud Virazel, Luigi Dilillo, Patrick Girard, 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2005, VLSI-SoC.

Effect-cause intra-cell diagnosis at transistor level

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2013, International Symposium on Quality Electronic Design (ISQED).

A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits

A. Bosio, P. Girard, A. Virazel, 2017, Journal of electronic testing.

Design space exploration and optimization of a Hybrid Fault-Tolerant Architecture

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2015, 2015 IEEE 21st International On-Line Testing Symposium (IOLTS).

Parity prediction synthesis for nano-electronic gate designs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010, 2010 IEEE International Test Conference.

SoC Yield Improvement - Using TMR Architectures for Manufacturing Defect Tolerance in Logic Cores

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010 .

Yield Improvement, Fault-Tolerance to the Rescue?

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2008, 2008 14th IEEE International On-Line Testing Symposium.

An effective hybrid fault-tolerant architecture for pipelined cores

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2015, 2015 20th IEEE European Test Symposium (ETS).

On Using Approximate Computing to Build an Error Detection Scheme for Arithmetic Circuits

V. Gherman, Patrick Girard, Arnaud Virazel, 2020, J. Electron. Test..

Comparison between random and pseudo-random generation for BIST of delay, stuck-at and bridging faults

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2000, Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646).

A statistical simulation method for reliability analysis of SRAM core-cells

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010, Design Automation Conference.

A Test Pattern Generation Technique for Approximate Circuits Based on an ILP-Formulated Pattern Selection Procedure

Arnaud Virazel, Alberto Bosio, Mario Barbareschi, 2019, IEEE Transactions on Nanotechnology.

Timing-aware ATPG for critical paths with multiple TSVs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014, 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

A Lightweight, Plug-and-Play and Autonomous JTAG Authentication IP for Secure Device Testing

A. Virazel, B. Rouzeyre, M. Flottes, 2022, 2022 IEEE European Test Symposium (ETS).

Emerging Computing Devices: Challenges and Opportunities for Test and Reliability*

Jürgen Teich, Muhammad Abdullah Hanif, Arnaud Virazel, 2021, 2021 IEEE European Test Symposium (ETS).

Multi-Level Control of Resistive RAM (RRAM) Using a Write Termination to Achieve 4 Bits/Cell in High Resistance State

Arnaud Virazel, Patrick Girard, Said Hamdioui, 2021, Electronics.

Maximizing Yield for Approximate Integrated Circuits

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Advanced Test Methods for SRAMs: Effective Solutions for Dynamic Fault Detection in Nanoscaled Technologies

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2009 .

A Capacitor-Less CMOS Neuron Circuit for Neuromemristive Networks

H. Aziza, M. Moreau, A Perez, 2019, 2019 17th IEEE International New Circuits and Systems Conference (NEWCAS).

Design, Verification, Test, and In-Field Implications of Approximate Digital Integrated Circuits

A. Bosio, P. Girard, A. Virazel, 2023 .

A Survey of Testing Techniques for Approximate Integrated Circuits

Alberto Bosio, Mario Barbareschi, Patrick Girard, 2020, Proceedings of the IEEE.

Design, Verification, Test and In-Field Implications of Approximate Computing Systems

A. Bosio, A. Savino, L. Sekanina, 2020, 2020 IEEE European Test Symposium (ETS).

Investigation of Mean-Error Metrics for Testing Approximate Integrated Circuits

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2018, 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

On the Comparison of Different ATPG Approaches for Approximate Integrated Circuits

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2018, 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Testing approximate digital circuits: Challenges and opportunities

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2018, 2018 IEEE 19th Latin-American Test Symposium (LATS).

Towards digital circuit approximation by exploiting fault simulation

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2017, 2017 IEEE East-West Design & Test Symposium (EWDTS).

Towards approximation during test of Integrated Circuits

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2017, 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Can we Approximate the Test of Integrated Circuits

Arnaud Virazel, Alberto Bosio, Mario Barbareschi, 2017 .

Analysis of resistive defects on a foundry 8T SRAM-based IMC architecture

P. Girard, A. Virazel, M. Flottes, 2023, Microelectronics Reliability.

High Defect Coverage with Low-Power Test Sequences in a BIST Environment

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2002, IEEE Des. Test Comput..

On using efficient test sequences for BIST

Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

Learning-Based Characterization Models for Quality Assurance of Emerging Memory Technologies

P. Girard, A. Virazel, Xhesila Xhafa, 2023, 2023 IEEE European Test Symposium (ETS).

On Using Cell-Aware Methodology for SRAM Bit Cell Testing

L. Anghel, P. Girard, A. Virazel, 2023, 2023 IEEE European Test Symposium (ETS).

Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology

Robin Wilson, Arnaud Virazel, Alberto Bosio, 2015, Sixteenth International Symposium on Quality Electronic Design.

Use of CCD to Detect Terrestrial Cosmic Rays at Ground Level: Altitude vs. Underground Experiments, Modeling and Numerical Monte Carlo Simulation

L. Dilillo, F. Wrobel, D. Munteanu, 2014, IEEE Transactions on Nuclear Science.

90 nm SRAM Static and Dynamic Mode Real-Time Testing at Concordia Station in Antarctica

G. Tsiligiannis, L. Dilillo, A. Bosio, 2014, IEEE Transactions on Nuclear Science.

A Memory Fault Simulator for Radiation-Induced Effects in SRAMs

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2010, 2010 19th IEEE Asian Test Symposium.

Evaluating a radiation monitor for mixed-field environments based on SRAM technology

Arnaud Virazel, Alberto Bosio, Luigi Dilillo, 2014 .

A Novel March Test Algorithm for Testing 8T SRAM-Based IMC Architectures

P. Girard, A. Virazel, M. Flottes, 2024, 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Electromigration Alleviation Techniques for 3D Integrated Circuits

M. Belleville, A. Bosio, P. Girard, 2017 .

Test of low power circuits: Issues and industrial practices

Arnaud Virazel, Alberto Bosio, Patrick Girard, 2016, 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS).