Eun-ae Chung

Technology scaling on High-K & Metal-Gate FinFET BTI reliability

M. Choe, Kyongtaek Lee, Wonchang Kang, 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

Spatial Distribution of Interface Traps in Sub-50-nm Recess-Channel-Type DRAM Cell Transistors

J. Moon, G. Jin, Y. Shin, 2011, IEEE Electron Device Letters.

Hole trap effect on time-dependent-dielectric breakdown (TDDB) of high-voltage peripheral nMOSFETs in flash memory application

Yoocheol Shin, Y. Shin, Eun-ae Chung, 2017, 2017 IEEE International Reliability Physics Symposium (IRPS).

Silicon nanowire-based tunneling field-effect transistors on flexible plastic substrates

Eun-ae Chung, Sangsig Kim, Myeongwon Lee, 2009, Nanotechnology.

Enhancement-mode silicon nanowire field-effect transistors on plastic substrates.

Eun-ae Chung, Sangsig Kim, Myeongwon Lee, 2009, Small.