C. Chuang

发表

Impact of NBTI and PBTI in SRAM bit-cells: Relative sensitivities and guidelines for application-specific target stability/performance

S. Zafar, J. Stathis, A. Bansal, 2009, 2009 IEEE International Reliability Physics Symposium.

Effects of gate-to-body tunneling current on pass-transistor based PD/SOI CMOS circuits

C. Chuang, R. Puri, 2002, 2002 IEEE International SOI Conference.

A 23-ps/2.1-mW ECL gate with an AC-coupled active pull-down emitter-follower stage

Ching-Te Chuang, James D. Warnock, Tze-Chiang Chen, 1989 .

Impacts of Random Telegraph Noise on FinFET devices, 6T SRAM cell, and logic circuits

C. Chuang, P. Su, M. Fan, 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

The impact of gate-oxide breakdown on SRAM stability

J. Stathis, B. Linder, A. Bhavnagarwala, 2002, IEEE Electron Device Letters.

Comparative Leakage Analysis of GeOI FinFET and Ge Bulk FinFET

C. Chuang, P. Su, M. Fan, 2013, IEEE Transactions on Electron Devices.

Ring oscillator circuit structures for measurement of isolated NBTI/PBTI effects

Ching-Te Chuang, S. Mukhopadhyay, S. Mukhopadhyay, 2008, 2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial.

Reliability monitoring ring oscillator structures for isolated/combined NBTI and PBTI measurement in high-k metal gate technologies

Barry P. Linder, Ching-Te Chuang, Chris H. Kim, 2011, 2011 International Reliability Physics Symposium.

Controlling floating-body effects for 0.13 /spl mu/m and 0.10 /spl mu/m SOI CMOS

Rajiv V. Joshi, Ching-Te Chuang, P. Oldiges, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

Bulk Ultrasonic Transducer Employing Piezoelectric Film on Thin Metal Sheet

R.M. White, C. Chuang, A. Lee, 1981, IEEE Transactions on Sonics and Ultrasonics.

FinFET SRAM Cell Optimization Considering Temporal Variability Due to NBTI/PBTI, Surface Orientation and Various Gate Dielectrics

C. Chuang, P. Su, M. Fan, 2011, IEEE Transactions on Electron Devices.

Performance and Stability Benchmarking of Monolithic 3-D Logic Circuits and SRAM Cells With Monolayer and Few-Layer Transition Metal Dichalcogenide MOSFETs

C. Chuang, P. Su, C. Yu, 2017, IEEE Transactions on Electron Devices.

Stability and Performance Optimization of Heterochannel Monolithic 3-D SRAM Cells Considering Interlayer Coupling

C. Chuang, P. Su, M. Fan, 2014, IEEE Transactions on Electron Devices.

Evaluation of Monolithic 3-D Logic Circuits and 6T SRAMs With InGaAs-n/Ge-p Ultra-Thin-Body MOSFETs

C. Chuang, P. Su, M. Fan, 2016, IEEE Journal of the Electron Devices Society.

Leakage-delay analysis of Ultra-Thin-Body GeOI devices and logic circuits

C. Chuang, P. Su, M. Fan, 2011, Proceedings of 2011 International Symposium on VLSI Technology, Systems and Applications.

Analysis of power-performance for Ultra-Thin-Body GeOI logic circuits

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

Random Dopant Fluctuation in Limited-Width FinFET Technologies

Ching-Te Chuang, Meng-Hsueh Chiang, Keunwoo Kim, 2007, IEEE Transactions on Electron Devices.

Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM array

Ming-Chien Tsai, Yi-Wei Lin, Hao-I Yang, 2012, Proceedings of Technical Program of 2012 VLSI Design, Automation and Test.

Self-Consistent and Efficient Electro-Thermal Analysis for Poly/Metal Gate FinFETs

Ching-Te Chuang, Keunwoo Kim, E. Nowak, 2006, 2006 International Electron Devices Meeting.

Analysis of GeOI FinFET 6T SRAM Cells With Variation-Tolerant WLUD Read-Assist and TVC Write-Assist

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2015, IEEE Transactions on Electron Devices.

Performance assessment of scaled strained-Si channel-on-insulator (SSOI) CMOS

Ching-Te Chuang, R. V. Joshi, Keunwoo Kim, 2002, 2002 IEEE International SOI Conference.

On the narrow-emitter effect of advanced shallow profile bipolar transistors

G. Li, T. Ning, T. Chen, 1987, 1987 International Electron Devices Meeting.

Physical compact model for threshold voltage in short-channel double-gate devices

Ching-Te Chuang, Keunwoo Kim, J. Fossum, 2003, International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003..

FinFET SRAM for high-performance low-power applications

I. Aller, T. Ludwig, E. Nowak, 2004, Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850).

Analysis and design of digital CMOS circuits in hybrid SOI-epitaxial technology with different crystal orientations

C. Chuang, K. Bernstein, S. Lo, 2004, 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).

Impact of Random Variations on Cell Stability and Write-Ability of Low-Voltage SRAMs Using Monolayer and Bilayer Transition Metal Dichalcogenide (TMD) MOSFETs

C. Chuang, P. Su, C. Yu, 2016, IEEE Electron Device Letters.

Static Noise Margin of Ultrathin-Body SOI Subthreshold SRAM Cells—An Assessment Based on Analytical Solutions of Poisson's Equation

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2009, IEEE Transactions on Electron Devices.

Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies

Kaushik Roy, Ching-Te Chuang, Saibal Mukhopadhyay, 2008, 21st International Conference on VLSI Design (VLSID 2008).

Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits

Kaushik Roy, Ching-Te Chuang, Saibal Mukhopadhyay, 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

Effect of reverse base current on bipolar and BiCMOS circuits

Ching-Te Chuang, Pong-Fei Lu, P. Lu, 1992 .

Investigation of BTI reliability for monolithic 3D 6T SRAM with ultra-thin-body GeOI MOSFETs

Ching-Te Chuang, Vita Pi-Ho Hu, Pin Su, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

On the effects of implantation of ions in the MeV energy range into silicon

L. K. Wang, G. P. Li, C. Chuang, 1986 .

Coupling of interdigital transducer to plate modes in a slotted acoustically-thin membrane

R.M. White, C. Chuang, 1983, IEEE Electron Device Letters.

Design and CAD challenges in sub-90nm CMOS technologies

C. Chuang, K. Bernstein, R. Joshi, 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

Ieee Vlsi Test Symposium

Melvin A. Breuer, Ching-Te Chuang, Edward J. McCluskey, 2011 .

Stability optimization of monolithic 3-D MoS2-n/WSe2-p SRAM cells for superthreshold and near-/sub-threshold applications

C. Chuang, P. Su, C. Yu, 2016, 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Analysis and modeling methodology of strained-Si channel-on-insulator (SSOI) MOSFETs

J. Cai, W. Haensch, K. Rim, 2003, 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672).

nd PBTI on Ultra-Thin-B 6T SRAM Cells

C. Chuang, P. Su, M. Fan, 2015 .

Performance evaluation of pass-transistor-based circuits using monolayer and bilayer 2-D transition metal dichalcogenide (TMD) MOSFETs for 5.9nm node

C. Chuang, P. Su, C. Yu, 2017, 2017 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

Performance benchmarking of monolayer and bilayer two-dimensional transition metal dichalcogenide (TMD) based logic circuits

C. Chuang, P. Su, C. Yu, 2016, 2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

Effects of Gate-to-Body Tunneling Current on PD/SOI CMOS Circuits

Ching-Te Chuang, K. Bernstein, R. Puri, 2001 .

Stability/performance assessment of monolithic 3D 6T/8T SRAM cells considering transistor-level interlayer coupling

C. Chuang, P. Su, M. Fan, 2014, Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

Nonquasi-static effects in saturated bipolar circuits

P. Lu, C. Chuang, B. Wu, 1994 .

Ultrahigh-Density 256-Channel Neural Sensing Microsystem Using TSV-Embedded Neural Probes

Shang-Lin Wu, Ching-Te Chuang, Wei Hwang, 2017, IEEE Transactions on Biomedical Circuits and Systems.

Yield estimation of SRAM circuits using “Virtual SRAM Fab”

Rouwaida Kanj, Fook-Luen Heng, Jin-Fuw Lee, 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

Novel high-density low-power high-performance double-gate logic techniques

C. Tretz, Ching-Te Chuang, Keunwoo Kim, 2004, 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).

An advanced high-performance trench-isolated self-aligned bipolar technology

M.B. Ketchen, T.H. Ning, G.P. Li, 1987, IEEE Transactions on Electron Devices.

PD/SOI SRAM performance in presence of gate-to-body tunneling current

Rajiv V. Joshi, Ching-Te Chuang, Fari Assaderaghi, 2003, IEEE Trans. Very Large Scale Integr. Syst..

Design considerations of scaled sub-0.1 /spl mu/m PD/SOI CMOS circuits

Rajiv V. Joshi, Ching-Te Chuang, Keunwoo Kim, 2003, Fourth International Symposium on Quality Electronic Design, 2003. Proceedings..

40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist

Ming-Hsien Tu, Shyh-Jye Jou, Ching-Te Chuang, 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

0 . 339 fJ / bit / search Energy-Efficient TCAM Macro Design in 40 nm LP CMOS

C. Chuang, Po-Tsang Huang, W. Hwang, 2014 .

Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies

Ching-Te Chuang, Saibal Mukhopadhyay, Rahul M. Rao, 2008, 2008 IEEE International Symposium on Circuits and Systems.

A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist

Chien-Yu Lu, Ming-Hsien Tu, Kuen-Di Lee, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

High performance MTCMOS technique for leakage reduction in hybrid SOI-epitaxial technologies with enhanced-mobility PFET header

Ching-Te Chuang, Shih-Hsien Lo, Koushik K. Das, 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

The Impact of Device Footprint Scaling on High-Performance CMOS Logic Technology

Ching-Te Chuang, Keunwoo Kim, Jie Deng, 2007, IEEE Transactions on Electron Devices.

Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI

Ching-Te Chuang, H.-S. Philip Wong, Keunwoo Kim, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist

Hao-I Yang, Ming-Hsien Tu, Nan-Chun Lien, 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

Low-Power Multiport SRAM With Cross-Point Write Word-Lines, Shared Write Bit-Lines, and Shared Write Row-Access Transistors

Ching-Te Chuang, Wei Hwang, Hon-Jarn Lin, 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing

Chien-Yu Lu, Ming-Chien Tsai, Ming-Hsien Tu, 2012, IEEE Journal of Solid-State Circuits.

Effects of processing conditions on the characteristics of platinum silicide Schottky barrier diodes

G. P. Li, C. Chuang, D. Moy, 1988 .

SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage

Ching-Te Chuang, Saibal Mukhopadhyay, Rahul M. Rao, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices

Kaushik Roy, Rajiv V. Joshi, Ching-Te Chuang, 2007, Microelectron. J..

Modeling and Analysis of Leakage Currents in Double-Gate Technologies

Kaushik Roy, Ching-Te Chuang, Saibal Mukhopadhyay, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

On the leverage of high-f/sub T/ transistors for advanced high-speed bipolar circuits

Ching-Te Chuang, Kenneth Chin, Emmanuel F. Crabbe, 1992 .

High-Density Reduced-Stack Logic Circuit Techniques Using Independent-Gate Controlled Double-Gate Devices

C. Tretz, Ching-Te Chuang, Meng-Hsueh Chiang, 2006, IEEE Transactions on Electron Devices.

Investigation of Backgate-Biasing Effect for Ultrathin-Body III-V Heterojunction Tunnel FET

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2015, IEEE Transactions on Electron Devices.

Impacts of work function variation and line edge roughness on hybrid TFET-MOSFET monolithic 3D SRAMs

Ching-Te Chuang, Pin Su, Jian-Hao Wang, 2017, 2017 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

Hysteresis effect in pass-transistor-based, partially depleted SOI CMOS circuits

Ching-Te Chuang, R. Puri, C. Chuang, 2000, IEEE Journal of Solid-State Circuits.

SOI for asynchronous dynamic circuits

Rajiv V. Joshi, Ching-Te Chuang, Wei Hwang, 2001, GLSVLSI '01.

Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits and 6T SRAM Cells

Ching-Te Chuang, Pin Su, Chang-Hung Yu, 2016, ISLPED.

A submicrometer high-performance bipolar technology

J.D. Cressler, D.D. Tang, T.H. Ning, 1989, IEEE Electron Device Letters.

Statistical Exploration of the Dual Supply Voltage Space of a 65nm PD/SOI CMOS SRAM Cell

Rouwaida Kanj, Ching-Te Chuang, Rajiv Joshi, 2006, 2006 European Solid-State Device Research Conference.

28nm 0.3V 1W2R Sub-Threshold FIFO Memory for Multi-Sensor IoT Applications

Ching-Te Chuang, Wei Hwang, Po-Tsang Huang, 2019, 2019 32nd IEEE International System-on-Chip Conference (SOCC).

28nm near/sub-threshold dual-port FIFO memory for shared queues in multi-sensor applications

Shang-Lin Wu, Ching-Te Chuang, Wei Hwang, 2018, 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

Evaluation of Monolayer and Bilayer 2-D Transition Metal Dichalcogenide Devices for SRAM Applications

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2016, IEEE Transactions on Electron Devices.

Circuit design techniques for the high-performance CMOS IBM S/390 Parallel Enterprise Server G4 microprocessor

Ching-Te Chuang, William V. Huott, James D. Warnock, 1997, IBM J. Res. Dev..

Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist

Ming-Chien Tsai, Ming-Hsien Tu, Shyh-Jye Jou, 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

Evaluation of Stability, Performance of Ultra-Low Voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell With Write-Assist Circuits

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2014, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Design and Analysis of Robust Tunneling FET SRAM

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2013, IEEE Transactions on Electron Devices.

0.4V Reconfigurable Near-Threshold TCAM in 28nm High-k Metal-Gate CMOS Process

Shang-Lin Wu, Ching-Te Chuang, Wei Hwang, 2018, 2018 31st IEEE International System-on-Chip Conference (SOCC).

Method for resolving simultaneous same-row access in Dual-Port 8T SRAM with asynchronous dual-clock operation

Wen-Rong Wu, Nan-Chun Lien, Ching-Te Chuang, 2013, 2013 IEEE International SOC Conference.

A disturb-free subthreshold 9T SRAM cell with improved performance and variation tolerance

Chien-Yu Lu, Ching-Te Chuang, C. Chuang, 2013, 2013 IEEE International SOC Conference.

Design of Sub-90 nm Low-Power and Variation Tolerant PD/SOI SRAM Cell Based on Dynamic Stability Metrics

Rajiv V. Joshi, Yue Tan, Ching-Te Chuang, 2009, IEEE Journal of Solid-State Circuits.

Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold SRAMs

Ching-Te Chuang, Chien-Yu Hsieh, Ming-Long Fan, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Schottky-barrier diode with self-aligned floating guard ring

R.D. Isaac, M. Arienzo, D. Tang, 1984, IEEE Transactions on Electron Devices.

On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits

Ching-Te Chuang, Richard B. Brown, Rahul M. Rao, 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit

Ching-Te Chuang, Richard B. Brown, Rahul M. Rao, 2008, 21st International Conference on VLSI Design (VLSID 2008).

Analysis of Single-Trap-Induced Random Telegraph Noise and its Interaction With Work Function Variation for Tunnel FET

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2013, IEEE Transactions on Electron Devices.

The effect of extrinsic base encroachment on the switch-on transient of advanced narrow-emitter bipolar transistors

Ching-Te Chuang, C. Chuang, 1988 .

Exploration and evaluation of low-dropout linear voltage regulator with FinFET, TFET and hybrid TFET-FinFET implementations

Ching-Te Chuang, Pin Su, Po-Tsang Huang, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

Novel Cu-to-Cu Bonding With Ti Passivation at 180 $^{\circ}{\rm C}$ in 3-D Integration

Ching-Te Chuang, Wei Hwang, Ho-Ming Tong, 2013, IEEE Electron Device Letters.

8T Single-ended sub-threshold SRAM with cross-point data-aware write operation

Ming-Hsien Tu, Shyh-Jye Jou, Ching-Te Chuang, 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

A double-sided, single-chip integration scheme using through-silicon-via for neural sensing applications

J. Chiou, Chih-Wei Chang, Kuan-Neng Chen, 2015, Biomedical microdevices.

On the current-voltage characteristics of n+-p-p+diodes

C. Chuang, 1983, IEEE Transactions on Electron Devices.

Comprehensive analysis of UTB GeOI logic circuits and 6T SRAM cells considering variability and temperature sensitivity

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2011, 2011 International Electron Devices Meeting.

On the punchthrough characteristics of advanced self-aligned bipolar transistors

E. Hackbarth, G.P. Li, C.T. Chuang, 1987, IEEE Transactions on Electron Devices.

A thin-membrane surface-acoustic-wave vapor-sensing device

J. Bernstein, C. Chuang, R. White, 1982, IEEE Electron Device Letters.

Band-to-Band-Tunneling Leakage Suppression for Ultra-Thin-Body GeOI MOSFETs Using Transistor Stacking

Ching-Te Chuang, Ming-Long Fan, Vita Pi-Ho Hu, 2012, IEEE Electron Device Letters.

Modeling and analysis of gate leakage in ultra-thin oxide sub-50nm double gate devices and circuits

Kaushik Roy, Rajiv V. Joshi, Ching-Te Chuang, 2005, Sixth international symposium on quality electronic design (isqed'05).

Excitation and Propagation of Plate Modes in an Acoustically-Thin Membrane

Richard M. White, C. Chuang, C. T. Chuang, 1982 .