Alex Settle

PIN: a binary instrumentation tool for computer architecture research and education

Vijay Janapa Reddi, Robert S. Cohn, Alex Settle, 2004, WCAE '04.

Dynamic run-time architecture techniques for enabling continuous optimization

Dirk Grunwald, Tipp Moseley, Vijay Janapa Reddi, 2005, CF '05.

A dynamically reconfigurable cache for multithreaded processors

Antonio González, Enric Gibert, Alex Settle, 2006, J. Embed. Comput..

Optimization for the Intel R Itanium R Architecture Register Stack

Alex Settle, Daniel A. Connors, Gerolf Hoflehner Dan Lavery, 2003 .

Optimization for the Intel/spl reg/ Itanium/spl reg/ architecture register stack

Daniel M. Lavery, Alex Settle, Daniel A. Connors, 2003, International Symposium on Code Generation and Optimization, 2003. CGO 2003..

Compiler Controlled Register Stack Management for the Intel R Itanium R Architecture

Alex Settle, Daniel A. Connors, Gerolf Hoflehner Dan Lavery, 2004 .

Optimization for the Intel® Itanium ®Architectur Register Stack

Daniel M. Lavery, Alex Settle, Daniel A. Connors, 2003, CGO.

Understanding the Impact of Inter-Thread Cache Interference on ILP in Modern SMT Processors

Alex Settle, Daniel A. Connors, Joshua L. Kihm, 2005, J. Instr. Level Parallelism.

Compiler-directed resource management for active code regions

Alex Settle, Daniel A. Connors, Ian Bratt, 2003, Seventh Workshop on Interaction Between Compilers and Computer Architectures, 2003. INTERACT-7 2003. Proceedings..

Architectural Support for Enhanced SMT Job Scheduling

Alex Settle, Daniel A. Connors, Joshua L. Kihm, 2004, IEEE PACT.