B. Davari

发表

A high performance 0.25 mu m CMOS technology

Y. Taur, K. Petrillo, B. Davari, 1988, Technical Digest., International Electron Devices Meeting.

Fabrication of CMOS on ultrathin SOI obtained by epitaxial lateral overgrowth and chemical-mechanical polishing

Y. Taur, T. Ning, T. Lii, 1990, International Technical Digest on Electron Devices.

A high-performance 0.25- mu m CMOS technology. II. Technology

Y. Taur, K. Petrillo, J. Sun, 1992 .

A new 'shift and ratio' method for MOSFET channel-length extraction

Y. Taur, P.J. Restle, G.G. Shahidi, 1992, IEEE Electron Device Letters.

Source—Drain contact resistance in CMOS with self-aligned TiSi2

Yuan Taur, Chung-Yu Ting, J. Sun, 1987, IEEE Transactions on Electron Devices.

A Room Temperature 0.1 /spl mu/m CMOS on SOI

J. Warnock, S. Furkay, D. Moy, 1993, Symposium 1993 on VLSI Technology.

A variable-size shallow trench isolation (STL) technology with diffused sidewall doping for submicron CMOS

Y. Taur, B. Davari, J. Warnock, 1988, Technical Digest., International Electron Devices Meeting.

Enhanced short-channel effects in NMOSFETs due to boron redistribution induced by arsenic source and drain implant

A. C. Warren, B. Davari, G. Shahidi, 1992, 1992 International Technical Digest on Electron Devices Meeting.

Transient Behavior of Transverse Acoustoelectric Voltage and Nondestructive Characterization of Semiconductor Surfaces

B. Davari, P. Das, 1985, IEEE Transactions on Sonics and Ultrasonics.

A study of the high resistivity GaAs surface and the GaAs/oxide interface using two‐beam transverse acousticoelectric voltage spectroscopy

B. Davari, P. Das, 1982 .

High performance 0.18 /spl mu/m SOI CMOS technology

M. Sherony, G. Biery, T.-C. Chen, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

Formation of Shallow Boron P + Junctions Using Sb Amorphization

D. Harame, G. Scilla, B. Davari, 1988 .

Voltage dependence of the MOSFET gate-to-source/drain overlap

Yuan Taur, B. Davari, Y. Taur, 1990 .

Boron redistribution in arsenic-implanted silicon and short-channel effects in metal-oxide-semiconductor field effect transistors

B. Davari, H. Hanafi, F. Cardone, 1992 .

A 0.22 /spl mu/m CMOS-SOI technology with a Cu BEOL

W. Rausch, D. Schepis, J. Sleight, 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

CMOS scaling in the 0.1-µm, 1.X-volt regime for high-performance applications

Tak H. Ning, Robert H. Dennard, James D. Warnock, 1995, IBM Journal of Research and Development.

A 0.18 /spl mu/m high-performance logic technology

S. Greco, M. Hargrove, X. Chen, 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

Electromigration Characteristics Under High Frequency Pulsed Current Stressing

B. Davari, T. Kwok, R. Kaufman, 1991 .

Electrical properties of semiconductor‐electrolyte (CdS‐NiCl2) using surface acoustic wave techniques

R. T. Webster, B. Davari, P. Das, 1979 .

CMOS scaling for high performance and low power-the next ten years

Robert H. Dennard, Ghavam G. Shahidi, Bijan Davari, 1995, Proc. IEEE.

Semiconductor surface characterization using transverse acoustoelectric voltage versus voltage measurements

B. Davari, P. Das, R. Bharat, 1983 .

Quenching and enhancement of the exciton and subband-gap absorption in GaAs:Cr using two-beam transverse acoustoelectric voltage spectroscopy

B. Davari, P. Das, 1982 .

Nondestructive evaluation of the semiconductor interface states' density using the transverse acoustoelectric voltage

B. Davari, P. Das, T. Liu, 1986 .

Characterization of Mercury Cadmium Telluride Using Nondestructive Transverse Acoustoelectric Voltage Measurements

B. Davari, M. Tabib-Azar, P. Das, 1983 .

Nondestructive evaluation of generation lifetime and surface generation velocity and the effect of etching, polishing and annealing on 5" Si wafer surface properties

B. Davari, M. Tabib-Azar, P. Das, 1983, 1983 International Electron Devices Meeting.

Semiconductor surface studies with SAW-oscillator structures

B. Davari, P. Das, R. Rademeyer, 1982 .

Profiling the Implanted Region in Si Using Nondestructive Transverse Acoustoelectric Voltage Versus Voltage Technique

B. Davari, P. Das, 1982 .

Gate materials consideration for submicron CMOS

B. Davari, C. Ting, 1989 .

Doping of n+ and p+ polysilicon in a dual-gate CMOS process

Yuan Taur, B. Davari, R. Angelucci, 1988 .

Indium channel implant for improved short-channel behavior of submicrometer NMOSFETs

B. Davari, B. Clark, P. Coane, 1993, IEEE Electron Device Letters.

Shallow p+ junction formation by a reverse‐type dopant preamorphization scheme

D. Harame, G. Scilla, B. Davari, 1989 .

Partially-depleted SOI technology for digital logic

E. Leobandung, G.G. Shahidi, F. Assaderaghi, 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

Scalability of SOI technology into 0.13 /spl mu/m 1.2 V CMOS generation

M. Sherony, J. Sleight, G. Shahidi, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

Saturation transconductance of deep-submicron-channel MOSFETs

Yuan Taur, Ghavam G. Shahidi, Bijan Davari, 1993 .

A high-performance 0.25- mu m CMOS technology. I. Design and characterization

Yuan Taur, Matthew R. Wordeman, W. H. Chang, 1992 .

A high-performance 0.08 /spl mu/m CMOS

E. Nowak, A. Ray, P. Agnello, 1996, 1996 Symposium on VLSI Technology. Digest of Technical Papers.

A High Performance 0.25/spl mu/m CMOS

J. Warnock, K. Jenkins, D. Klaus, 1993, Symposium 1993 on VLSI Technology.

Workload and network-optimized computing systems

Hubertus Franke, David P. LaPotin, Shahrokh Daijavad, 2010, IBM J. Res. Dev..

A novel high-performance lateral bipolar on SOI

Y. Taur, D.D. Tang, B. Davari, 1991, International Electron Devices Meeting 1991 [Technical Digest].