J. Bucchignano

发表

A high performance 0.25 mu m CMOS technology

Y. Taur, K. Petrillo, B. Davari, 1988, Technical Digest., International Electron Devices Meeting.

Triple-self-aligned, planar double-gate MOSFETs: devices and circuits

J. Treichler, K. Guarini, G. Cohen, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Two-dimensional pattern formation using graphoepitaxy of PS-b-PMMA block copolymers for advanced FinFET device and circuit fabrication.

Chi-Chun Liu, Hsinyu Tsai, Sarunya Bangsaruntip, 2014, ACS nano.

High Performance Long-and Short-Channel In0.7Ga0.3As-channel MOSFETs

J. Bucchignano, G. Shahidi, E. Kiewra, 2008, 2008 Device Research Conference.

High-Performance $\hbox{In}_{0.7}\hbox{Ga}_{0.3}\hbox{As}$ -Channel MOSFETs With High-$\kappa$ Gate Dielectrics and $\alpha$-Si Passivation

J. Bucchignano, G. Shahidi, E. Kiewra, 2009, IEEE Electron Device Letters.

Scaling of In0.7Ga0.3As buried-channel MOSFETs

Yanning Sun, J. Bucchignano, G. Shahidi, 2008, 2008 IEEE International Electron Devices Meeting.

Lithography and fabrication processes for sub‐100 nm scale complementary metal–oxide semiconductor

Yuan Taur, J. J. Bucchignano, Shalom J. Wind, 1995 .

Ultrasonic and dip resist development processes for 50 nm device fabrication

J. Bucchignano, R. Viswanathan, R. Viswanathan, 1997 .

Extendibility of NiPt silicide to the 22-nm node CMOS technology

Anna W. Topol, K. Ohuchi, V. Narayanan, 2008, Extended Abstracts - 2008 8th International Workshop on Junction Technology (IWJT '08).

Sub-50 nm half-pitch imaging with a low activation energy chemically amplified photoresist

Martha I. Sanchez, Gregory M. Wallraff, William D. Hinsberg, 2004 .

Resist contrast enhancement in high resolution electron beam lithography

S. Wind, J. Bucchignano, F. Hohn, 1989 .

Spatially Confined Chemistry: Fabrication of Ge Quantum Dot Arrays

J. Heath, S. Wind, J. Bucchignano, 1996 .

Design and characterization of compact 100 nm‐scale silicon metal–oxide–semiconductor field effect transistors

J. Keller, S. Wind, R. Volant, 1992 .

High mobility III–V channel MOSFETs for post-Si CMOS applications

S. Koester, D. Webb, J. Bucchignano, 2009, 2009 IEEE International Conference on IC Design and Technology.

A comparison of C54-TiSi 2 formation in blanket and submicron gate structures using in situ x-ray diffraction during rapid thermal annealing

J. Jordan-Sweet, C. Cabral, J. Bucchignano, 1995 .

TiSi 2 Formation on Submicron Polysilicon Lines: Role of Line Width and Dopant Concentration

S. Wind, J. Bucchignano, R. Assenza, 1993 .

In situ x‐ray diffraction analysis of the C49–C54 titanium silicide phase transformation in narrow lines

G. Morales, Lawrence A. Clevenger, Karl F. Ludwig, 1995 .

Simple fabrication scheme for sub-10 nm electrode gaps using electron-beam lithography

Richard Martel, J. J. Bucchignano, Josef Michl, 2002 .

Hybrid lithography: The marriage between optical and e-beam lithography. A method to study process integration and device performance for advanced device nodes

Steven E. Steen, Sharee J. McNab, Lidija Sekaric, 2006 .

Two gates are better than one [double-gate MOSFET process]

J. Benedict, J. Treichler, H.-S.P. Wong, 2003, IEEE Circuits and Devices Magazine.

Extendibility of NiPt Silicide Contacts for CMOS Technology Demonstrated to the 22-nm Node

Anna W. Topol, M. Khare, C. Lavoie, 2007, 2007 IEEE International Electron Devices Meeting.

Observation of magnetic switching in submicron magnetic-tunnel junctions at low frequency

S. Parkin, J. Bucchignano, P. Trouilloud, 1999 .

Intrinsically ultrastrong plasmon–exciton interactions in crystallized films of carbon nanotubes

Douglas M. Bishop, P. Avouris, J. Bucchignano, 2018, Proceedings of the National Academy of Sciences.

High performance 0.1 /spl mu/m CMOS devices with 1.5 V power supply

Yuan Taur, Keith A. Jenkins, P. J. Coane, 1993, Proceedings of IEEE International Electron Devices Meeting.

Graphene radio frequency devices on flexible substrate

Keith A. Jenkins, Wenjuan Zhu, Phaedon Avouris, 2013 .

Hydrogen silsesquioxane-based hybrid electron beam and optical lithography for high density circuit prototyping

Josephine B. Chang, E. Joseph, W. Haensch, 2009 .

Sharp Reduction of Contact Resistivities by Effective Schottky Barrier Lowering With Silicides as Diffusion Sources

W. Haensch, C. Lavoie, J. Newbury, 2010, IEEE Electron Device Letters.

Pattern collapse mitigation strategies for EUV lithography

Robert L. Bruce, Michael A. Guillorn, Dario L. Goldfarb, 2012, Advanced Lithography.

Two-dimensional pattern formation using graphoepitaxy of PS-b-PMMA block copolymers for advanced FinFET device and circuit fabrication.

Joy Y. Cheng, E. Joseph, J. Pitera, 2014, ACS nano.

High chi block copolymer DSA to improve pattern quality for FinFET device fabrication

Chi-Chun Liu, C. Grant Willson, Christopher J. Ellison, 2016, SPIE Advanced Lithography.

Self-aligned line-space pattern customization with directed self-assembly graphoepitaxy at 24nm pitch

Markus Brink, Joy Cheng, Michael A. Guillorn, 2015, Advanced Lithography.

Pattern transfer of directed self-assembly patterns for CMOS device applications

Sebastian Engelmann, Joy Cheng, Michael A. Guillorn, 2013 .

Sub-30 nm pitch line-space patterning of semiconductor and dielectric materials using directed self-assembly

Sebastian Engelmann, Joy Cheng, Michael A. Guillorn, 2012 .