M. Véstias

发表

Multi-core for K-means clustering on FPGA

Horácio C. Neto, Mario Vestias, Jose Canilho, 2016, 2016 26th International Conference on Field Programmable Logic and Applications (FPL).

Floating-Point Single-Precision Fused Multiplier-adder Unit on FPGA

Ana Rita Silva, M. Véstias, H. Neto, 2014 .

Using SystemC to Model and Simulate a Many-Core Architecture for LU Decomposition

Ana Rita Silva, M. Véstias, H. Neto, 2014 .

Convolutional Neural Network

Mario Vestias, M. Véstias, 2020, Programming with TensorFlow.

Deep Learning on Edge

Mario Vestias, M. Véstias, 2020, Smart Systems Design, Applications, and Challenges.

A Survey of Convolutional Neural Networks on Edge with Reconfigurable Computing

Mário P. Véstias, M. Véstias, 2019, Algorithms.

FPGA-based architecture for hyperspectral endmember extraction

José M. P. Nascimento, Mario Vestias, João Rosário, 2014, Remote Sensing.

Viterbi Decoder in Hardware

Mário Pereira Vestias, M. Véstias, 2019, Advances in Computer and Electrical Engineering.

Fast Convolutional Neural Networks in Low Density FPGAs Using Zero-Skipping and Weight Pruning

Horácio C. Neto, Rui Policarpo Duarte, Mario Vestias, 2019, Electronics.

A Review of Synthetic-Aperture Radar Image Formation Algorithms and Implementations: A Computational Perspective

M. Véstias, H. Neto, R. Duarte, 2022, Remote. Sens..

FPGA-based Architecture for Hyperspectral Compressive Sensing

M. Véstias, J. Nascimento, 2021, 2021 Telecoms Conference (ConfTELE).

FPGA-based architecture for hyperspectral unmixing

Mário P. Véstias, José M. P. Nascimento, Gabriel Martín, 2015, 2015 IEEE International Geoscience and Remote Sensing Symposium (IGARSS).

Hyperspectral Compressive Sensing With a System-On-Chip FPGA

José M. P. Nascimento, Gabriel Martin, Mário Véstias, 2020, IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing.

System-on-chip field-programmable gate array design for onboard real-time hyperspectral unmixing

José M. P. Nascimento, Mario Vestias, M. Véstias, 2016 .

Moving Deep Learning to the Edge

Horácio C. Neto, Rui Policarpo Duarte, Mario Vestias, 2020, Algorithms.

A Many-Core Co-Processor for Embedded Parallel Computing on FPGA

Wilson Jose, Horacio Neto, Mario Vestias, 2015, 2015 Euromicro Conference on Digital System Design.

A Configurable Architecture for Running Hybrid Convolutional Neural Networks in Low-Density FPGAs

Mário P. Véstias, Horácio C. Neto, Rui P. Duarte, 2020, IEEE Access.

Onboard Processing of Synthetic Aperture Radar Backprojection Algorithm in FPGA

Pedro R. Miranda, M. Véstias, H. Neto, 2022, IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing.

Trends of CPU, GPU and FPGA for high-performance computing

Mário P. Véstias, Horácio C. Neto, M. Véstias, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

Modeling and Simulation of a Many-core Architecture Using SystemC

Horácio C. Neto, Mario Vestias, Ana Rita Silva, 2014 .

Efficient Design of Pruned Convolutional Neural Networks on FPGA

Mario Vestias, M. Véstias, 2020, Journal of Signal Processing Systems.

A Full Featured Configurable Accelerator for Object Detection With YOLO

Mário P. Véstias, Horácio C. Neto, João D. Lopes, 2021, IEEE Access.

Router Design for Application Specific Networks-on-Chip on Reconfigurable Systems

Mário P. Véstias, Horácio C. Neto, M. Véstias, 2007, 2007 International Conference on Field Programmable Logic and Applications.

Area and performance optimization of a generic network-on-chip architecture

Mário P. Véstias, Horácio C. Neto, M. Véstias, 2006, SBCCI '06.

A Generic Network-on-Chip Architecture for Reconfigurable Systems: Implementation and Evaluation

Mário P. Véstias, Horácio C. Neto, M. Véstias, 2006, 2006 International Conference on Field Programmable Logic and Applications.

Area/Performance Improvement of NoC Architectures

Mário P. Véstias, Horácio C. Neto, M. Véstias, 2006, ARC.

Co-synthesis of a configurable SoC platform based on a network on chip architecture

Mário P. Véstias, Horácio C. Neto, M. Véstias, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Algorithm-oriented design of efficient many-core architectures applied to dense matrix multiplication

Ana Rita Silva, M. Véstias, H. Neto, 2014, Analog Integrated Circuits and Signal Processing.

Algorithm-oriented design of efficient many-core architectures applied to dense matrix multiplication

Mário P. Véstias, Horácio C. Neto, Ana Rita Silva, 2015 .

DALI: a methodology for the co-design of dataflow applications on hardware/software architectures [video encoder DSP example]

Mário P. Véstias, Horácio C. Neto, M. Véstias, 2003, 16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings..

System-level co-synthesis of dataflow dominated applications on reconfigurable hardware/software architectures

Mário P. Véstias, Horácio C. Neto, M. Véstias, 2002, Proceedings 13th IEEE International Workshop on Rapid System Prototyping.