T. Chakraborty

Built in self test: a complete test solution for telecommunication systems

Nilanjan Mukherjee, Ramesh Karri, Tapan J. Chakraborty, 1999, IEEE Commun. Mag..

Novel DFTs for Circuit Initialization to Reduce Functional Fmax Test Time

Ujjwal Guin, T. Chakraborty, M. Tehranipoor, 2013 .

On behavior fault modeling for combinational digital designs

Sumit Ghosh, Tapan J. Chakraborty, Sumit Ghosh, 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

A Robust Architecture for Flip-Flops Tolerant to Soft-Errors and Transients from Combinational Circuits

Tapan J. Chakraborty, Aditya Jagirdar, Roystein Oliveira, 2008, 21st International Conference on VLSI Design (VLSID 2008).

A TMR Scheme for SEU Mitigation in Scan Flip-Flops

Tapan J. Chakraborty, Aditya Jagirdar, Roystein Oliveira, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

On behavior fault modeling for digital designs

Sumit Ghosh, Tapan J. Chakraborty, Sumit Ghosh, 1991, J. Electron. Test..

Gentest: an automatic test-generation system for sequential circuits

Wu-Tung Cheng, Tapan J. Chakraborty, T. Chakraborty, 1989, Computer.

Design for Testability for Path Delay Faults in Sequential Circuits

Vishwani D. Agrawal, Michael L. Bushnell, Tapan J. Chakraborty, 1993, 30th ACM/IEEE Design Automation Conference.

Enhanced controllability for IDDQ test sets using partial scan

Chih-Jen Lin, Sudipta Bhawmik, Tapan J. Chakraborty, 1991, 28th ACM/IEEE Design Automation Conference.

The architecture of the GenTest sequential test generator

S. Davidson, T. J. Chakraborty, Robert Bencivenga, 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.