C. Shi

发表

G. Shi, Bo Hu, C. Shi, 2004 .

Parallel and distributed VHDL simulation

C. Shi, D. Lungeanu, 2000, Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537).

VHDL-AMS based modeling and simulation of mixed-technology microsystems: a tutorial

C.-J. Richard Shi, Pavel V. Nikitin, P. Nikitin, 2007, Integr..

FROSTY: a fast hierarchy extractor for industrial CMOS circuits

C. Shi, Lei Yang, 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

SILCA: fast-yet-accurate time-domain simulation of VLSI circuits with strong parasitic coupling effects

C. Shi, Z. Li, 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

Exact and Heuristic Minimization of Determinant Decision Diagrams

C. Shi, S. Wa, A. Manthe, 2002 .

Rapid Frequency-domain Analog Fault Simulation Under Parameter Tolerances

C. Shi, M. Tian, 1997, Proceedings of the 34th Design Automation Conference.

SILCA: SPICE-accurate iterative linear-centric analysis for efficient time-domain Simulation of VLSI circuits with strong parasitic couplings

Zhao Li, C.-J. Richard Shi, Zhao Li, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Graph Reduction Approach to Symbolic Circuit Analysis

C.-J. Richard Shi, Weiwei Chen, Guoyong Shi, 2007, 2007 Asia and South Pacific Design Automation Conference.

Sliced Message Passing: High Throughput Overlapped Decoding of High-Rate Low-Density Parity-Check Codes

C.-J. Richard Shi, Lingzhi Liu, C. Shi, 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

Model-order reduction by dominant subspace projection: error bound, subspace computation, and circuit applications

C.-J. Richard Shi, Guoyong Shi, G. Shi, 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

A quasi-Newton preconditioned Newton-Krylov method for robust and efficient time-domain simulation of integrated circuits with strong parasitic couplings

Zhao Li, C.-J. Richard Shi, Zhao Li, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Template-Based Parasitic-Aware Optimization and Retargeting of Analog and RF Integrated Circuit Layouts

S. Bhattacharya, Lihong Zhang, N. Jangkrajarng, 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

Template-driven parasitic-aware optimization of analog integrated circuit layouts

C.-J. Richard Shi, Sambuddha Bhattacharya, Nuttorn Jangkrajarng, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Correct-by-construction layout-centric retargeting of large analog designs

C.-J. Richard Shi, Roy Hartono, Sambuddha Bhattacharya, 2004, Proceedings. 41st Design Automation Conference, 2004..

Multiple specifications radio-frequency integrated circuit design with automatic template-driven layout retargeting

C. Shi, N. Jangkrajarng, S. Bhattacharya, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

IPRAIL - intellectual property reuse-based analog IC layout automation

C.-J. Richard Shi, Roy Hartono, Sambuddha Bhattacharya, 2003, Integr..

MCAST: an abstract-syntax-tree based model compiler for circuit simulation

Bo Wan, C.-J.R. Shi, L. Zhou, 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

CASCADE: A Standard Supercell Design Methodology With Congestion-Driven Placement for Three-Dimensional Interconnect-Heavy Very Large-Scale Integrated Circuits

C.-J. Richard Shi, Lili Zhou, Cherry Wakayama, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Maximizing the throughput-area efficiency of fully-parallel low-density parity-check decoding with C-slow retiming and asynchronous deep pipelining

C.-J. Richard Shi, Ming Su, Lili Zhou, 2007, 2007 25th International Conference on Computer Design.

Implementing a 2-Gbs 1024-bit ½-rate low-density parity-check code decoder in three-dimensional integrated circuits

Bo Hu, C.-J. Richard Shi, Lili Zhou, 2007, 2007 25th International Conference on Computer Design.

Code construction and FPGA implementation of a low-error-floor multi-rate low-density Parity-check code decoder

Lei Yang, Hui Liu, C.-J. Richard Shi, 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

Cycle elimination method to construct VLSI oriented LDPC codes

Lei Yang, C.-J.R. Shi, Hiu Liu, 2005, VTC-2005-Fall. 2005 IEEE 62nd Vehicular Technology Conference, 2005..

Efficient DC fault simulation of nonlinear analog circuits: one-step relaxation and adaptive simulation continuation

Guoyong Shi, C.-J.R. Shi, M. W. Tian, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Analog building block design in 14nm FinFET using inversion coefficient

A. Wang, V. Dhawan, C.-J R. Shi, 2014, 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Efficient approximation of symbolic expressions for analog behavioral modeling and analysis

Sheldon X.-D. Tan, C.-J. Richard Shi, C. Shi, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Simulation and sensitivity of linear analog circuits under parameter variations by Robust interval analysis

C.-J. Richard Shi, Michael W. Tian, C. Shi, 1999, TODE.

Automatic test generation of linear analog circuits under parameter variations

C.-J. Richard Shi, Michael W. Tian, C. Shi, 1998, Proceedings of 1998 Asia and South Pacific Design Automation Conference.

Non-Monte Carlo Simulation and Sensitivity of Linear(ized) Analog Circuits under Parameter Variations*

C.-J. Richard Shi, Michael W. Tian, C. Shi, 1997 .

Automatic analog layout retargeting for new processes and device sizes

C.-J. Richard Shi, Roy Hartono, Sambuddha Bhattacharya, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

Interpretable symbolic small-signal characterization of large analog circuits using determinant decision diagrams

Sheldon X.-D. Tan, C.-J. Richard Shi, C. Shi, 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

Hierarchical symbolic analysts of large analog circuits with determinant decision diagrams

C.-J.R. Shi, Xiangdong Tan, C. Shi, 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

Symbolic analysis of large analog circuits with determinant decision diagrams

C. Shi, S. Tan, 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

Layout compaction for yield optimization via critical area minimization

C. Shi, C.-J.R. Shi, Y. Bourai, 2000, Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537).

Parametric reduced order modeling for interconnect analysis

G. Shi, C. Shi, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

Efficient DDD-based term generation algorithm for analog circuit behavioral modeling

S.X.-D. Tan, C. Shi, S. Tan, 2003, Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003..

Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings

Xiang-Dong Tan, Li-Pen Yuan, D. Lungeanu, 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).