T. Kwasniewski

发表

Delta-sigma modulation in fractional-N frequency synthesis

T. Riley, M. Copeland, T. Kwasniewski, 1993 .

CMOS high-speed dual-modulus frequency divider for RF frequency synthesis

T. Kwasniewski, Navid Foroudi, 1995 .

A monolithic 10-Gb/s CMOS limiting amplifier for low cost optical communication systems

Bo Wang, Dianyong Chen, Bangli Liang, 2008, 2008 14th Asia-Pacific Conference on Communications.

4 GHz RF DOWN-CONVERSION MIXERS IN STANDARD CMOS TECHNOLOGY

Arif A. Siddiqi, T. Kwasniewski, 2009 .

A 3.3 GHz LC-based digitally controlled oscillator with 5kHz frequency resolution

T. Kwasniewski, J. Zhuang, Q. Du, 2007, 2007 IEEE Asian Solid-State Circuits Conference.

Prediction of phase noise in CMOS distributed oscillators

Jing Zhang, Tad Kwasniewski, Haitao Mei, 2003, Proceedings of the 2003 SBMO/IEEE MTT-S International Microwave and Optoelectronics Conference - IMOC 2003. (Cat. No.03TH8678).

Delta-Sigma Modulation in

M. A. Copeland, Tom A. D. Riley, Tad Kwasniewski, 1993 .

A 1.25 GHz 0.35 /spl mu/m monolithic CMOS PLL clock generator for data communications

Tad Kwasniewski, Lizhong Sun, T. Kwasniewski, 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).

A Fast CMOS Self-Oscillating Modulator for RF Power Amplifier

T. Kwasniewski, X. Wang, 2007, 2007 Canadian Conference on Electrical and Computer Engineering.

0.18 Lm Cmos Backplane Receiver with Decision-feedback Equalisation Embedded

T. Kwasniewski, W. Huang, S. Wang, 2000 .

A delay-locked frequency synthesizer with low phase noise performance

T. Kwasniewski, J. Zhuang, Q. Du, 2003, 2003 IEEE Conference on Electron Devices and Solid-State Circuits (IEEE Cat. No.03TH8668).

A quadrature output voltage controlled ring oscillator based on three-stage sub-feedback loops

Krzysztof Iniewski, Tad A. Kwasniewski, Lizhong Sun, 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

A 1.25-GHz 0.35-μm monolithic CMOS PLL based on a multiphase ring oscillator

Lizhong Sun, T. A. Kwasniewski, T. Kwasniewski, 2001, IEEE J. Solid State Circuits.

CMOS VCOs for PLL frequency synthesis in GHz digital mobile radio communications

M. Thamsirianunt, Tad Kwasniewski, T. Kwasniewski, 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.

Inductorless oscillator design for personal communications devices-a 1.2 /spl mu/m CMOS process case study

T. Kwasniewski, M. Abou-Seido, A. Bouchet, 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.

A 1.2 /spl mu/m CMOS implementation of a low-power 900-MHz mobile radio frequency synthesizer

T.A. Kwasniewski, M. Thamsirianunt, T. Kwasniewski, 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.

Recent advances in high-speed serial I/O trends, standards and techniques

T. Kwasniewski, P. Noel, F. Zarkeshvari, 2005, Canadian Conference on Electrical and Computer Engineering, 2005..

On-die power grid broadband model determination using a priori narrowband measurements

Tad Kwasniewski, Xin Jie Wang, Leonard MacEachem, 2017, 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS).

Low noise CMOS voltage-control oscillator design methodology with emphasis on non-linear effect contributions, 2.4 GHz CMOS design example

Zhe Jiang, Tad A. Kwasniewski, Haizheng Guo, 2015, 2015 IEEE 28th Canadian Conference on Electrical and Computer Engineering (CCECE).

Design and comparison of CMOS Current Mode Logic latches

Muhammad Usama, Tad A. Kwasniewski, T. Kwasniewski, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

Optimal equalization for reducing the impact of channel group delay distortion on high-speed backplane data transmission

Lei Zhang, Tadeusz Kwasniewski, T. Kwasniewski, 2010 .

On /spl Delta//spl Sigma/ fractional-N frequency synthesizers

T. Kwasniewski, F. Zarkeshvari, P. Noel, 2005, International Symposium on Signals, Circuits and Systems, 2005. ISSCS 2005..

Design and implementation of a Multiplierless Reconfigurable DFT/DCT processor

V. Szwarc, T. Kwasniewski, H. Ho, 2009, 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference.

A novel CMOS edge equalizer for 10-GB/S highly lossy backplane

Bo Wang, Dianyong Chen, Bangli Liang, 2008, 2008 24th Biennial Symposium on Communications.