G. Shahidi

发表

Electron velocity overshoot at 300 K and 77 K in silicon MOSFETs with submicron channel lengths

H.I. Smith, D. Antoniadis, G. Shahidi, 1986, 1986 International Electron Devices Meeting.

Fabrication of CMOS on ultrathin SOI obtained by epitaxial lateral overgrowth and chemical-mechanical polishing

Y. Taur, T. Ning, T. Lii, 1990, International Technical Digest on Electron Devices.

Advanced gate stacks with fully silicided (FUSI) gates and high-/spl kappa/ dielectrics: enhanced performance at reduced gate leakage

H. Nayfeh, M. Ieong, J. Kedzierski, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

A new 'shift and ratio' method for MOSFET channel-length extraction

Y. Taur, P.J. Restle, G.G. Shahidi, 1992, IEEE Electron Device Letters.

A Room Temperature 0.1 /spl mu/m CMOS on SOI

J. Warnock, S. Furkay, D. Moy, 1993, Symposium 1993 on VLSI Technology.

Band-Edge High-Performance High-k/Metal Gate n-MOSFETs Using Cap Layers Containing Group IIA and IIIB Elements with Gate-First Processing for 45 nm and Beyond

M. Ieong, E. Cartier, V. Narayanan, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Impact of the gate-to-body tunneling current on SOI history effect

M. Sherony, G. Shahidi, L. Wagner, 2000, 2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125).

Controlling floating-body effects for 0.13 /spl mu/m and 0.10 /spl mu/m SOI CMOS

Rajiv V. Joshi, Ching-Te Chuang, P. Oldiges, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

Enhanced short-channel effects in NMOSFETs due to boron redistribution induced by arsenic source and drain implant

A. C. Warren, B. Davari, G. Shahidi, 1992, 1992 International Technical Digest on Electron Devices Meeting.

High Performance Long-and Short-Channel In0.7Ga0.3As-channel MOSFETs

J. Bucchignano, G. Shahidi, E. Kiewra, 2008, 2008 Device Research Conference.

High-Performance $\hbox{In}_{0.7}\hbox{Ga}_{0.3}\hbox{As}$ -Channel MOSFETs With High-$\kappa$ Gate Dielectrics and $\alpha$-Si Passivation

J. Bucchignano, G. Shahidi, E. Kiewra, 2009, IEEE Electron Device Letters.

Ultrathin Strained-Ge Channel P-MOSFETs With High-$K$ /Metal Gate and Sub-1-nm Equivalent Oxide Thickness

J. Hoyt, Y. Zhu, G. Shahidi, 2012, IEEE Electron Device Letters.

Scaling of In0.7Ga0.3As buried-channel MOSFETs

Yanning Sun, J. Bucchignano, G. Shahidi, 2008, 2008 IEEE International Electron Devices Meeting.

High performance 0.18 /spl mu/m SOI CMOS technology

M. Sherony, G. Biery, T.-C. Chen, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

Anomalous voltage overshoot during turn-off of thin-film n-channel SOI MOSFETs

E. Dubois, E. Dubois, G. Shahidi, 1993, IEEE Electron Device Letters.

Electron velocity overshoot at room and liquid nitrogen temperatures in silicon inversion layers

H.I. Smith, D. Antoniadis, G. Shahidi, 1988, IEEE Electron Device Letters.

SOI: opportunities and challenges for sub-0.25 mu m VLSI

G. Shahidi, 1992, Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting.

Extendibility of NiPt silicide to the 22-nm node CMOS technology

Anna W. Topol, K. Ohuchi, V. Narayanan, 2008, Extended Abstracts - 2008 8th International Workshop on Junction Technology (IWJT '08).

Poly-Si/high-k gate stacks with near-ideal threshold voltage and mobility

P. Oldiges, K. Maitra, V. Narayanan, 2005, IEEE VLSI-TSA International Symposium on VLSI Technology, 2005. (VLSI-TSA-Tech)..

Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS

T. Nagumo, N. Loubet, W. Schwarzenbach, 2012, 2012 Symposium on VLSI Technology (VLSIT).

A 0.22 /spl mu/m CMOS-SOI technology with a Cu BEOL

W. Rausch, D. Schepis, J. Sleight, 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

A Low-Power Thin-Film Si Heterojunction FET Noise Amplifier for Generation of True Random Numbers

Bahman Hekmatshoar, Ghavam G. Shahidi, G. Shahidi, 2019, IEEE Journal of the Electron Devices Society.

Demonstration of Symmetric Lateral NPN Transistors on SOI Featuring Epitaxially Grown Emitter/Collector Regions

Kevin K. H. Chan, T. Ning, P. Hashemi, 2018, IEEE Journal of the Electron Devices Society.

CMOS scaling in the 0.1-µm, 1.X-volt regime for high-performance applications

Tak H. Ning, Robert H. Dennard, James D. Warnock, 1995, IBM Journal of Research and Development.

Reliability issues for silicon-on-insulator

M. Khare, D. Badami, T. Hook, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

High mobility III–V channel MOSFETs for post-Si CMOS applications

S. Koester, D. Webb, J. Bucchignano, 2009, 2009 IEEE International Conference on IC Design and Technology.

Implant approaches and challenges for 20nm node and beyond ETSOI devices

M. Khare, S. Luning, B. Haran, 2011, IEEE 2011 International SOI Conference.

Silicon Nanowire Field Effect Transistor Sensors with Minimal Sensor-to-Sensor Variations and Enhanced Sensing Characteristics.

Heike Riel, Ghavam Shahidi, Sufi Zafar, 2018, ACS nano.

CMOS scaling for high performance and low power-the next ten years

Robert H. Dennard, Ghavam G. Shahidi, Bijan Davari, 1995, Proc. IEEE.

SOI technology for the GHz era

G. G. Shahidi, G. Shahidi, 2001, 2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517).

Extendibility of NiPt Silicide Contacts for CMOS Technology Demonstrated to the 22-nm Node

Anna W. Topol, M. Khare, C. Lavoie, 2007, 2007 IEEE International Electron Devices Meeting.

An anomalous correlation between gate leakage current and threshold voltage fluctuation in advanced MOSFETs

W. Haensch, G. Shahidi, K. Rim, 2010, 2010 International Electron Devices Meeting.

SOI at IBM: current status of technology, modeling, design, and the outlook for the 0.1 /spl mu/m generation

G. Shahidi, Fariborz Assaderaghi, G. Shahidi, 2000, 2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125).

Reduction of channel hot-electron-generated substrate current in sub-150-nm channel length Si MOSFET's

D. Antoniadis, G. Shahidi, D.A. Antoniadis, 1988, IEEE Electron Device Letters.

Electron velocity overshoot in sub-100-nm channel length metal-oxide-semiconductor field-effect transistors at 77 and 300 K

Henry I. Smith, D. Antoniadis, G. Shahidi, 1988 .

Uniaxial strain relaxation on ultra-thin strained-Si directly on insulator (SSDOI) substrates

C. Sung, M. Khare, M. Ieong, 2006, 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings.

Indium channel implant for improved short-channel behavior of submicrometer NMOSFETs

B. Davari, B. Clark, P. Coane, 1993, IEEE Electron Device Letters.

High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET

M. Vinet, L. Grenouillet, T. Nagumo, 2012, 2012 International Electron Devices Meeting.

Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications

B. Jagannathan, N. Loubet, P. Kulkarni, 2010, Proceedings of 2010 International Symposium on VLSI Technology, System and Application.

Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond

Junjun Li, Davood Shahrjerdi, Robert Gauthier, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

Partially-depleted SOI technology for digital logic

E. Leobandung, G.G. Shahidi, F. Assaderaghi, 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

Scalability of SOI technology into 0.13 /spl mu/m 1.2 V CMOS generation

M. Sherony, J. Sleight, G. Shahidi, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

Saturation transconductance of deep-submicron-channel MOSFETs

Yuan Taur, Ghavam G. Shahidi, Bijan Davari, 1993 .

Mainstreaming of SOI Technology

G.G. Shahidi, G. Shahidi, 1999, 29th European Solid-State Device Research Conference.

Dust‐Sized High‐Power‐Density Photovoltaic Cells on Si and SOI Substrates for Wafer‐Level‐Packaged Small Edge Computers

C. Cabral, J. Ott, G. Shahidi, 2020, Advanced materials.

Inversion mode n-channel GaAs field effect transistor with high-k/metal gate

D. Webb, R. Germann, G. Shahidi, 2008 .

Submicron‐gap high‐mobility silicon picosecond photodetectors

E. Ippen, J. Melngailis, G. Shahidi, 1985 .

Impact of back bias on ultra-thin body and BOX (UTBB) devices

M. Vinet, T. Skotnicki, L. Grenouillet, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

A novel high-performance lateral bipolar on SOI

Y. Taur, D.D. Tang, B. Davari, 1991, International Electron Devices Meeting 1991 [Technical Digest].

Silicon-on-insulator dynamic threshold ESD networks and active clamp circuitry

M. Sherony, D. Dreps, S. Voldman, 2000, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476).

Silicon-on-insulator dynamic threshold ESD networks and active clamp circuitry ☆

Ghavam G. Shahidi, Steven H. Voldman, Robert Russell Williams, 2002 .

Analysis and Characterization of Rib Waveguides and Multiple-Guide Couplers

L. Molter-Orr, M. Kuznetsov, M. Islam, 2022 .

Photorefractive Effect Joint Services Electronics Program ( Contract DAAG 29-83-K-0003 )

Phillips, M. J., H. Haus, 2009 .