R. Baird

发表

Linearity enhancement of multibit /spl Delta//spl Sigma/ A/D and D/A converters using data weighted averaging

R. Baird, T. Fiez, 1995 .

A Low Oversampling Ratio 14b 500-kHz ADC with a Self-Calibrated Multibit DAC

Terri S. Fiez, Rex T. Baird, R. Baird, 1996 .

Linearity enhancement of multibit delta-sigma A/D and D/A converters using data weighted averaging

R. T. Baird, R. Baird, 1995 .

Improved Delta-Sigma DAC Linearity Using Data Weighted Averaging.

Terri S. Fiez, Rex T. Baird, R. Baird, 1995 .

A 2.5-Gb/s Multi-Rate 0.25-$\mu$m CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition

Qicheng Yu, B.W. Garlepp, M.H. Perrott, 2006, IEEE Journal of Solid-State Circuits.

A 2.5Gb/s Multi-Rate 0.25/spl mu/m CMOS CDR Utilizing a Hybrid Analog/Digital Loop Filter

B.W. Garlepp, M.H. Perrott, Ligang Zhang, 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.