C. Seger

发表

Introduction to generalized symbolic trajectory evaluation

Carl-Johan H. Seger, Jin Yang, Jin Yang, 2003, IEEE Trans. Very Large Scale Integr. Syst..

Formally Verifying IEEE Compliance of Floating-Point Hardware

C. Seger, John E. O Leary, Xudong Zhao, 2022 .

Formal verification using parametric representations of Boolean constraints

Carl-Johan H. Seger, Mark Aagaard, Robert B. Jones, 1999, DAC '99.

Compositional Model Checking of Partially Ordered State Spaces

S. Hazelhurst, C. Seger, 1996 .

Stately: An FSM Design Tool.

C. Seger, J. Pope, Jules Saget, 2020, 2020 18th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE).

Cephalopode: A custom processor aimed at functional language execution for IoT devices.

C. Seger, J. Pope, Jules Saget, 2020, 2020 18th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE).

Symbolic trajectory evaluation for word-level verification: theory and implementation

C. Seger, Supratik Chakraborty, Z. Khasidashvili, 2017, Formal Methods Syst. Des..

The formal verification of a pipelined double-precision IEEE floating-point multiplier

Carl-Johan H. Seger, Mark Aagaard, C. Seger, 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

High level architectural modelling for early estimation of power and performance

Mary Sheeran, Wouter Swierstra, Koen Claessen, 2009 .

Practical Formal Verification in Microprocessor Design

Carl-Johan H. Seger, Mark Aagaard, Robert B. Jones, 2001, IEEE Des. Test Comput..

An industrially effective environment for formal hardware verification

Carl-Johan H. Seger, Mark Aagaard, Robert B. Jones, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Generalized Symbolic Trajectory Evaluation - Abstraction in Action

Carl-Johan H. Seger, Jin Yang, Jin Yang, 2002, FMCAD.

A simple theorem prover based on symbolic trajectory evaluation and BDD's

Carl-Johan H. Seger, Scott Hazelhurst, S. Hazelhurst, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Advances in asynchronous circuit theory. Part I : gate and unbounded inertial delay

J. A Brzozowski, C.J.H. Seger, J. Brzozowski, 1990 .

Formal verification by symbolic evaluation of partially-ordered trajectories

Randal E. Bryant, Carl-Johan H. Seger, R. Bryant, 1995, Formal Methods Syst. Des..

Formal Verification of Digital Circuits Using Symbolic Ternary System Models

Randal E. Bryant, Carl-Johan H. Seger, R. Bryant, 1990, CAV.

Lifted-FL: A Pragmatic Implementation of Combined Model Checking and Theorem Proving

Carl-Johan H. Seger, Mark Aagaard, Robert B. Jones, 1999, TPHOLs.

The HOL-Voss System: Model-Checking inside a General-Purpose Theorem-Prover

Jeffrey J. Joyce, Carl-Johan H. Seger, C. Seger, 1993, HUG.

Formal hardware verification by symbolic ternary trajectory evaluation

Randal E. Bryant, Carl-Johan H. Seger, Derek L. Beatty, 1991, 28th ACM/IEEE Design Automation Conference.

A Mathematically Precise Two-Level Formal Hardware Verification Methodology*

Jeffrey J. Joyce, Carl Carl-Johan Seger, C. Seger, 1992 .

A Two-Level Formal Verification Methodology using HOL and COSMOS

Jeffrey J. Joyce, Carl-Johan H. Seger, C. Seger, 1991, CAV.

Compositional Specification and Model Checking in GSTE

Carl-Johan H. Seger, Jin Yang, Jin Yang, 2004, CAV.

Formal verification of iterative algorithms in microprocessors

Carl-Johan H. Seger, Mark Aagaard, Roope Kaivola, 2000, Proceedings 37th Design Automation Conference.

Self-Consistency Checking

David L. Dill, Carl-Johan H. Seger, Robert B. Jones, 1996, FMCAD.

Symbolic Trajectory Evaluation

Carl-Johan H. Seger, Scott Hazelhurst, S. Hazelhurst, 1997, Formal Hardware Verification.

Electronic Workshops in Computing Designing Correct Circuits an Integrated Approach to Verifying Large Circuits: a Case Study an Integrated Approach to Verifying Large Circuits : a Case Study

S. Hazelhurst, C. J.-H. Seger, M. Sheeran, 2022 .

Linking BDD-Based Symbolic Evaluation to Interactive Theorem-Proving

Jeffrey J. Joyce, Carl-Johan H. Seger, C. Seger, 1993, 30th ACM/IEEE Design Automation Conference.

Higher Order Logic Theorem Proving and Its Applications

Michael J. C. Gordon, Luc Claesen, C. Seger, 1994, Lecture Notes in Computer Science.

Introduction to generalized symbolic trajectory evaluation

Carl-Johan H. Seger, Jin Yang, Jin Yang, 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.

A bounded delay race model

Carl-Johan H. Seger, C. Seger, 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.