W. Lee

BSIM4 gate leakage model including source-drain partition

C. Hu, K. Cao, W. Lee, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

A novel CVD-SiBCN Low-K spacer technology for high-speed applications

W. Lee, C. Ko, T. Kuan, 2008, 2008 Symposium on VLSI Technology.

Density-gradient simulations of quantum effects in ultra-thin-oxide MOS structures

R. Dutton, M. Ancona, W. Lee, 1997, SISPAD '97. 1997 International Conference on Simulation of Semiconductor Processes and Devices. Technical Digest.

Substrate-strained silicon technology: process integration [CMOS technology]

Y. Yeo, S. Chen, C. Hu, 2003, IEEE International Electron Devices Meeting 2003.

Simulation of quantum confinement effects in ultra-thin-oxide MOS structures

R. Dutton, M. Ancona, W. Lee, 1996, Journal of Technology Computer Aided Design TCAD.

A fully planar p-n-p heterojunction bipolar transistor

P. Dapkus, W. Lee, K. Dzurko, 1988, IEEE Electron Device Letters.

Novel Diffusion Topography Engineering (DTE) for High Performance CMOS Applications

W. Y. Teo, C. Kuo, W. Lee, 2007, 2007 IEEE International Electron Devices Meeting.

NiSi Schottky Barrier Process-Strained Si (SB-PSS) CMOS Technology for High Performance Applications

J.W. Hsu, C.H. Ko, C.H. Ge, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..