H. Amano

发表

RHINET: a network for high performance parallel computing using locally distributed computers

H. Amano, O. Tatebe, T. Kudoh, 1999, Innovative Architecture for Future Generation High-Performance Processors and Systems (Cat. No.PR00650).

Impulse: a high performance processing unit for multiprocessors for scientific calculation

H. Amano, T. Boku, S. Nomura, 1988, [1988] The 15th Annual International Symposium on Computer Architecture. Conference Proceedings.

VLAN-based minimal paths in PC cluster with Ethernet on mesh and torus

A. Jouraku, H. Amano, Tomohiro Otsuka, 2005, 2005 International Conference on Parallel Processing (ICPP'05).

Architecture and Evaluation of a Third-Generation RHiNET Switch for High-Performance Parallel Computing

Hideharu Amano, Hiroaki Nishi, Tomohiro Kudoh, 2003 .

An I/O mechanism on a dynamically reconfigurable processor - which should be moved: data or configuration?

Hideharu Amano, Yohei Hasegawa, Shohei Abe, 2005, International Conference on Field Programmable Logic and Applications, 2005..

Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor

Vu Manh Tuan, H. Amano, Takuro Nakamura, 2006, Proceedings 20th IEEE International Parallel & Distributed Processing Symposium.

Application-Based Performance and Power Analysis on Dynamically Reconfigurable Processor

Vu Manh Tuan, H. Amano, Takuro Nakamura, 2005 .

ffi cient Data TLB Design for Embedded Processors

H. Amano, M. Namiki, Zhao Lei, 2010 .

Implementation and evaluation of self-organizing map algorithm on a graphic processor

Hideharu Amano, Masato Yoshimi, Yuri Nishikawa, 2009 .

Session details: First international workshop on highly-efficient accelerators and reconfigurable technologies (HEART)

Hideharu Amano, Wayne Luk, W. Luk, 2010, CARN.

Gain-switching of GaInN multiquantum well laser diodes

I. White, R. Penty, Shih-Yuan Wang, 2000 .

Geyser: Energy-Efficient MIPS CPU Core with Fine-Grained Run-Time Power Gating

Hiroshi Sasaki, Hideharu Amano, Kimiyoshi Usami, 2012 .

Performance Improvement by a Multicast Mechanism For a Massively Parallel Processor JUMP-1

Hideharu Amano, Masahiro Goshima, Katsunobu Nishimura, 2001 .

XX A Co-Processor Design for an Energy Efficient Reconfigurable Accelerator

H. Amano, Cma, M. Izawa, 2014 .

Performance Evaluation of a Prototype of RHiNET-2: A Network-based Distributed Parallel Computing System

Hideharu Amano, Hiroshi Harada, Hiroaki Nishi, 2003, Applied Informatics.

Parallel processing system using network - connected PCs

Mitsuhisa Sato, Hideharu Amano, Osamu Tatebe, 1999 .

Design of cellular simulation platform for SBML model

Hiroaki Kitano, Yuichiro Shibata, Hideharu Amano, 2005 .

Improving the Performance of Circuit-Switched Interconnection Network for a Multi-FPGA System

H. Amano, M. Koibuchi, Kohe Ito, 2021, IEICE Trans. Inf. Syst..

A Multi-Tenant Resource Management System for Multi-FPGA Systems

Akram Ben Ahmed, Ryousei Takano, H. Amano, 2021, IEICE Trans. Inf. Syst..

Interconnection Network and Distributed Shared Memory of a Massively Parallel Machine Jump-1

H. Nishi, H. Amano, K. Nishimura, 2007 .

Making and Evaluation of the Compiler for WASMII, a Virtual hardware system

Yuichiro Shibata, Hideharu Amano, Keisuke Iwai, 1998 .

Total System Image of the Reconfigurable Machine WASMII

Yuichiro Shibata, Hideharu Amano, Xiao-ping Ling, 1997, International Conference on Parallel and Distributed Processing Techniques and Applications.

Evaluation of Embedded Chip Multi-Processors using Parallelized MiBench Suits

Hideharu Amano, Yasuki Tanabe, Masato Sumiyosi, 2006 .

Preliminary evaluation of batch-learning self-organizing map algorithm on a graphic processor

Hideharu Amano, Toshimichi Ikemura, Takashi Abe, 2010 .

Performance and cost evaluations of on-chip network topologies in FPGAs (リコンフィギャラブルシステム)

Hideharu Amano, Hiroki Matsutani, Michihiro Koibuchi, 2009 .

A Parametric Study of Packet-Switched FPGA Overlay Networks

Hideharu Amano, Hiroki Matsutani, Michihiro Koibuchi, 2006 .

A study on snoop cache systems for single-chip multiprocessors

Hideharu Amano, Keisuke Inoue, Takuya Terasawa, 1997, Systems and Computers in Japan.

Evaluation of a multicore reconfigurable architecture (リコンフィギャラブルシステム)

Hideharu Amano, Hiroki Matsutani, Vu Manh Tuan, 2009 .

HOBONET: AN INTER-PU CONNECTION NETWORK WITH FAULT-TOLERANCY.

Hideharu Amano, Takashi Yokota, Hideo Aiso, 1984 .

COMPATIBLE ACKNOWLEDGING ETHERNET.

Hideharu Amano, Mario Tokoro, Toshitada Saito, 1987 .

Implementation of Data Driven Applications on a Multi-Context Reconfigurable Device

Yuichiro Shibata, Hideharu Amano, Masaki Uno, 2003 .

A link removal methodology for application-specific (リコンフィギャラブルシステム)

Hideharu Amano, Hiroki Matsutani, Michihiro Koibuchi, 2008 .

A Fault Diagnosis and Recovery Technique for a Batcher Sorter

Hideharu Amano, H. Amano, 1992 .

Future reconfigurable computing system

Hideharu Amano, S. Trimberger, M. Motomura, 2004, ASP-DAC.

A Low-Power Fault-Tolerant NoC using Error Correction and Detection Codes

Hideharu Amano, Hiroki Matsutani, Michihiro Koibuchi, 2010 .

Extracting Success from IBM’s 20-Qubit Machines Using Error-Aware Compilation

Hideharu Amano, Rodney Van Meter, Takahiko Satoh, 2019, ACM J. Emerg. Technol. Comput. Syst..

FPGA-based accelerator for losslessly quantized convolutional neural networks

Hideharu Amano, Ryosuke Kazami, Mankit Sit, 2017, 2017 International Conference on Field Programmable Technology (ICFPT).

A Simple Data Transfer Technique Using Local Address for Networks-on-Chips

Hideharu Amano, Yutaka Yamada, Michihiro Koibuchi, 2006, IEEE Transactions on Parallel and Distributed Systems.

Black-Bus: a new data-transfer technique using local address on networks-on-chips

Hideharu Amano, Yutaka Yamada, Michihiro Koibuchi, 2004, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings..

FPGA-Based HPRC for Bioinformatics Applications

Hideharu Amano, Yoshiki Yamaguchi, Yasunori Osana, 2013 .

Adaptive Flux Calculation Scheme in Advection Term Computation Using Partial Reconfiguration

Hideharu Amano, Naoyuki Fujita, Takayuki Akamine, 2013, Int. J. Netw. Comput..

Scalable deep neural network accelerator cores with cubic integration using through chip interface

Hiroshi Nakamura, Hideharu Amano, Jun Ishii, 2017, 2017 International SoC Design Conference (ISOCC).

The Design and Implementation of Scalable Deep Neural Network Accelerator Cores

Hiroshi Nakamura, Hideharu Amano, Jun Ishii, 2017, 2017 IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC).

Optimizing Application Mapping for Multi-FPGA Systems with Multi-ejection STDM Switches

H. Amano, Ryota Yasudo, Kohe Ito, 2022, 2022 32nd International Conference on Field-Programmable Logic and Applications (FPL).

A Batcher Double Omega Network with Combining

Kalidou Gaye, Hideharu Amano, H. Amano, 1992, ICPP.

(SM)²-II: A Large-Scale Multiprocessor for Sparse Matrix Calculations

Taisuke Boku, Hideharu Amano, Tomohiro Kudoh, 1990, IEEE Trans. Computers.

A Shared Memory Architecture for MANJI Production System Machine

Kenji Takeda, Hideharu Amano, Jun Miyazaki, 1987, IWDM.

An implementation methodology for Neural Network on a Low-end FPGA Board

H. Amano, Kaijie Wei, Koki Honda, 2020, 2020 Eighth International Symposium on Computing and Networking (CANDAR).

A Practical Collision Avoidance Method for an Inter-Chip Bus with Wireless Inductive through Chip Interface

Tadahiro Kuroda, Hideharu Amano, Junichiro Kadomoto, 2017, 2017 Fifth International Symposium on Computing and Networking (CANDAR).

RT-libSGM: An Implementation of a Real-time Stereo Matching System on FPGA

H. Amano, Kaijie Wei, Yukinori Kuno, 2022, HEART.

FPGA Design for Autonomous Vehicle Driving Using Binarized Neural Networks

Hideharu Amano, Koki Honda, Kaijie Wei, 2018, 2018 International Conference on Field-Programmable Technology (FPT).

Multi-objective Optimization for Application Mapping and Body Bias Control on a CGRA

Hideharu Amano, Hayate Okuhara, Nguyen Anh Vu Doan, 2017, 2017 IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC).

FPL Demo: An FPGA-IP Prototype Chip for MEC devices

H. Amano, M. Iida, M. Kuga, 2022, International Conference on Field-Programmable Logic and Applications.

Body bias control for renewable energy source with a high inner resistance

H. Amano, Hayate Okuhara, Keita Azegami, 2018, International Symposium on Low-Power and High-Speed Chips.

Power Optimization Methodology for Ultralow Power Microcontroller With Silicon on Thin BOX MOSFET

Hideharu Amano, Hayate Okuhara, Yu Fujita, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A 297mops/0.4mw ultra low power coarse-grained reconfigurable accelerator CMA-SOTB-2

Hideharu Amano, Hayate Okuhara, Yu Fujita, 2015, 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig).

An optimal power supply and body bias voltage for a ultra low power micro-controller with silicon on thin box MOSFET

Hideharu Amano, Hayate Okuhara, Yu Fujita, 2015, 2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips

Hiroshi Nakamura, Hideharu Amano, Kimiyoshi Usami, 2011, IEEE Micro.

k-Optimized Path Routing for High-Throughput Data Center Networks

Hideharu Amano, Ryuta Kawano, Hiroki Matsutani, 2018, 2018 Sixth International Symposium on Computing and Networking (CANDAR).

FiC-RNN: A Multi-FPGA Acceleration Framework for Deep Recurrent Neural Networks

Hideharu Amano, Yuxi Sun, H. Amano, 2020, IEICE Trans. Inf. Syst..

Horizontal division of deep learning applications with all-to-all communication on a multi-FPGA system

Akram Ben Ahmed, H. Amano, Kensuke Iizuka, 2020, 2020 Eighth International Symposium on Computing and Networking Workshops (CANDARW).

Performance Estimation for Exascale Reconfigurable Dataflow Platforms

Hideharu Amano, Wayne Luk, Tobias Becker, 2018, 2018 International Conference on Field-Programmable Technology (FPT).

Analytical Performance Estimation for Large-Scale Reconfigurable Dataflow Platforms

Hideharu Amano, Wayne Luk, Ana Lucia Varbanescu, 2021, ACM Transactions on Reconfigurable Technology and Systems.

An FPGA Acceleration for the Kd-tree Search in Photon Mapping

Hideharu Amano, Masato Yoshimi, Takuya Kuhara, 2013, ARC.

Neural network parallel computing for multi-layer channel routing problems

Yoshiyasu Takefuji, Hideharu Amano, Kyotaro Suzuki, 1995, Neurocomputing.

FPGA Acceleration of ROS2-Based Reinforcement Learning Agents

H. Amano, Midori Sugaya, Takeshi Ohkawa, 2020, 2020 Eighth International Symposium on Computing and Networking Workshops (CANDARW).

In-switch approximate processing: Delayed tasks management for MapReduce applications

Hideharu Amano, Hiroki Matsutani, Michihiro Koibuchi, 2017, 2017 27th International Conference on Field Programmable Logic and Applications (FPL).

RHiNET-3/SW: an 80-Gbit/s high-speed network switch for distributed parallel computing

Hideharu Amano, Hiroaki Nishi, Tomohiro Kudoh, 2001, HOT 9 Interconnects. Symposium on High Performance Interconnects.

64-Gb/s highly reliable network switch (RHiNET-2/SW) using parallel optical interconnection

S. Nishimura, N. Matsudaira, H. Amano, 2000, Journal of Lightwave Technology.

A network switch using optical interconnection for high performance parallel computing using PCs: High-density implementation of high-speed signals for a one-chip electronic switch with optical interconnections

Hideharu Amano, Hiroaki Nishi, S. Nishimura, 1999, Proceedings. 6th International Conference on Parallel Interconnects (PI'99) (Formerly Known as MPPOI).

Acceleration of Deep Recurrent Neural Networks with an FPGA cluster

Hideharu Amano, Akram Ben Ahmed, YuXi Sun, 2019, HEART 2019.

HOSMII: A Virtual Hardware Integrated with DRAM

Yuichiro Shibata, Hideharu Amano, Xiao-ping Ling, 1998, IPPS/SPDP Workshops.

SNAIL: A Multiprocessor Based on the Simple Serial Synchronized Multistage Interconnection Network Architecture

Kalidou Gaye, Hideharu Amano, Jun Terada, 1994, 1994 International Conference on Parallel Processing Vol. 1.

Ultralow-voltage design and technology of silicon-on-thin-buried-oxide (SOTB) CMOS for highly energy efficient electronics in IoT era

Hideharu Amano, Kazutoshi Kobayashi, Kimiyoshi Usami, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology

Hideharu Amano, Duc-Hung Le, Cong-Kha Pham, 2014, 2014 IEEE COOL Chips XVII.

Principles and Structures of FPGAs

Hideharu Amano, H. Amano, 2018, Springer Singapore.

From FLOPS to BYTES: Disruptive Change towards the Post-Moore Era (Unrefereed Workshop Manuscript)

Satoshi Matsuoka, Hideharu Amano, Toshio Endo, 2016 .

From FLOPS to BYTES: disruptive change in high-performance computing towards the post-moore era

Satoshi Matsuoka, Takahiro Katagiri, Hideharu Amano, 2016, Conf. Computing Frontiers.

Recursive Diagonal Torus: an interconnection network for massively parallel computers

Hideharu Amano, Yulu Yang, Toshinori Sueyoshi, 1993, Proceedings of 1993 5th IEEE Symposium on Parallel and Distributed Processing.

Hardware-resource Utilization Analysis on an FPGA-Based Biochemical Simulator ReCSiP

Hiroaki Kitano, Yuichiro Shibata, Hideharu Amano, 2006 .

Efficient scheduling of rate law functions for ODE-based multimodel biochemical simulation on an FPGA

Hiroaki Kitano, Yuichiro Shibata, Kiyoshi Oguri, 2005, International Conference on Field Programmable Logic and Applications, 2005..

Implementation of Bitsliced AES Encryption on CUDA-Enabled GPU

Hideharu Amano, Keisuke Iwai, Naoki Nishikawa, 2017, NSS.

Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs

Hiroshi Nakamura, Hideharu Amano, Kimiyoshi Usami, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

GenMap: A Genetic Algorithmic Approach for Optimizing Spatial Mapping of Coarse-Grained Reconfigurable Architectures

Hideharu Amano, Nguyen Anh Vu Doan, Takuya Kojima, 2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

The First 25 Years of the FPL Conference

Marco Platzner, Viktor K. Prasanna, Hideharu Amano, 2017, ACM Trans. Reconfigurable Technol. Syst..

Towards an Optimized Multi FPGA Architecture with STDM Network: A Preliminary Study

Hideharu Amano, Kazuei Hironaka, Ng. Anh Vu Doan, 2018, ARC.

(SM)2-II: a new version of the sparse matrix solving machine

Taisuke Boku, Hideharu Amano, Tomohiro Kudoh, 1985, ISCA '85.

A Scalable Body Bias Optimization Method Toward Low-Power CGRAs

H. Amano, Masaaki Kondo, Takuya Kojima, 2023, IEEE Micro.

Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs

Hiroshi Nakamura, Hideharu Amano, Kimiyoshi Usami, 2010, 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip.

Prediction router: Yet another low latency on-chip router architecture

Hideharu Amano, Tsutomu Yoshinaga, Hiroki Matsutani, 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

TCI Tester: A Chip Tester for Inductive Coupling Wireless Through-Chip Interface

H. Amano, Hideto Kayashima, 2023, Journal of Low Power Electronics and Applications.

Design of a low power NoC router using Marching Memory Through type

Hideharu Amano, Masashi Watanabe, Tadao Nakamura, 2014, 2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS).

Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface

Tadahiro Kuroda, Hideharu Amano, Junichiro Kadomoto, 2018, Int. J. Netw. Comput..

3D NoC with Inductive-Coupling Links for Building-Block SiPs

Daisuke Sasaki, Tadahiro Kuroda, Hideharu Amano, 2014, IEEE Transactions on Computers.

Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces

Tadahiro Kuroda, Hideharu Amano, Hiroki Matsutani, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A metamorphotic Network-on-Chip for various types of parallel applications

Hideharu Amano, Hiroki Matsutani, Michihiro Koibuchi, 2015, 2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP).

Run-time power gating of on-chip routers using look-ahead routing

Hideharu Amano, Hiroki Matsutani, Michihiro Koibuchi, 2008, 2008 Asia and South Pacific Design Automation Conference.

Body bias control for a coarse grained reconfigurable accelerator implemented with Silicon on Thin BOX technology

Hideharu Amano, Yu Fujita, Honlian Su, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

A case for random shortcut topologies for HPC interconnects

Henri Casanova, Hideharu Amano, D. Frank Hsu, 2012, 2012 39th Annual International Symposium on Computer Architecture (ISCA).

Key-value Store Chip Design for Low Power Consumption

Hideharu Amano, Hiroki Matsutani, Yuta Tokusashi, 2019, 2019 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS).

CubeSim: A Cycle Accurate Simulator for Multicore System with 3D SiP∗

H. Amano, Takuya Kojima, Takeharu Ikezoe, 2021 .

Implementation of FM-Index Based Pattern Search on a Multi-FPGA System

Hideharu Amano, Akram Ben Ahmed, M. M. Imdad Ullah, 2020, ARC.

A Deadlock-Free Non-minimal Fully Adaptive Routing Using Virtual Cut-Through Switching

Hideharu Amano, Hiroki Matsutani, Michihiro Koibuchi, 2010, 2010 IEEE Fifth International Conference on Networking, Architecture, and Storage.

An Effective Design of Deadlock-Free Routing Algorithms Based on 2D Turn Model for Irregular Networks

Hideharu Amano, Michihiro Koibuchi, Akiya Jouraku, 2007, IEEE Transactions on Parallel and Distributed Systems.

Performance evaluation of deterministic routings, multicasts, and topologies on RHiNET-2 cluster

Hideharu Amano, Tomohiro Otsuka, Konosuke Watanabe, 2005, IEEE Transactions on Parallel and Distributed Systems.

II. Multiprocessor System Architectures

Hideharu Amano, H. Amano, 1993 .

Path selection algorithm: the strategy for designing deterministic routing from alternative paths

Hideharu Amano, Michihiro Koibuchi, Akiya Jouraku, 2005, Parallel Comput..

MMLRU Selection Function: A Simple and Efficient Output Selection Function in Adaptive Routing

Hideharu Amano, Michihiro Koibuchi, Akiya Jouraku, 2005, IEICE Trans. Inf. Syst..

Performance evaluation of routing algorithms in RHiNET-2 cluster

Hideharu Amano, Konosuke Watanabe, Michihiro Koibuchi, 2003, 2003 Proceedings IEEE International Conference on Cluster Computing.

Martini: A Network Interface Controller Chip for High Performance Computing with Distributed PCs

Hideharu Amano, Noboru Tanabe, Hiroaki Nishi, 2007, IEEE Transactions on Parallel and Distributed Systems.

Removing Context Memory from a Multi-context Dynamically Reconfigurable Processor

Hideharu Amano, Masayuki Kimura, Nobuaki Ozaki, 2012, 2012 IEEE 6th International Symposium on Embedded Multicore SoCs.

Power reduction techniques for Dynamically Reconfigurable Processor Arrays

Takashi Nishimura, Hideharu Amano, Vasutan Tunbunheng, 2008, 2008 International Conference on Field Programmable Logic and Applications.

The performance of SNAIL-2 (a SSS-MIN connected multiprocessor with cache coherent mechanism)

H. Amano, T. Hanawa, Yasuki Tanabe, 2005, Parallel Comput..

NDL: A LANGUAGE FOR SOLVING SCIENTIFIC PROBLEMS ON MIMD MACHINES.

Taisuke Boku, Hideharu Amano, Tomohiro Kudoh, 1985 .

A static scheduling system for a parallel machine (SM)2-II

Hideharu Amano, Xiao-ping Ling, H. Amano, 1989, PARLE.

An Adaptable Cluster Structure of (SM)²-II

Hideharu Amano, Tomohiro Kudoh, Hideo Aiso, 1986, CONPAR.

Cache Controller Design on Ultra Low Leakage Embedded Processors

Hideharu Amano, Lei Zhao, Hui Xu, 2009, ARCS.

MAPLE chip: a processing element for a static scheduling centric multiprocessor

H. Amano, Keisuke Iwai, K. Yasufuku, 2003, Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003..

The preliminary evaluation of MBP-light with two protocol policies for a massively parallel processor-JUMP-1

Hideharu Amano, Junji Yamamoto, K. Anjo, 1999, Proceedings. Frontiers '99. Seventh Symposium on the Frontiers of Massively Parallel Computation.

A Performance Evaluation of the Multiprocessor Testbed ATTEMPT-0

Hideharu Amano, Tomohiro Kudoh, Takuya Terasawa, 1995, Parallel Comput..

Vegeta: An Implementation and Evaluation of Development-Support Middleware on Multiple OpenCL Platform

Hideharu Amano, Masato Yoshimi, Masahiro Yamada, 2011, 2011 Second International Conference on Networking and Computing.

Applying FPGA to Sound Separation by Direction-Pass Filter

Hiroaki Kitano, Hideharu Amano, Kazuhiro Nakadai, 2003 .

Designing low‐diameter interconnection networks with multi‐ported host‐switch graphs

Hideharu Amano, Michihiro Koibuchi, Koji Nakano, 2020, Concurr. Comput. Pract. Exp..

Designing High-Performance Interconnection Networks with Host-Switch Graphs

Hideharu Amano, Hiroki Matsutani, Michihiro Koibuchi, 2019, IEEE Transactions on Parallel and Distributed Systems.

A Layout-Oriented Routing Method for Low-Latency HPC Networks

Hideharu Amano, Ryuta Kawano, Hiroki Matsutani, 2017, IEICE Trans. Inf. Syst..

XYZ-Randomization using TSVs for low-latency energy efficient 3D-NoCs

Hideharu Amano, Hiroshi Nakahara, Ng. Anh Vu Doan, 2017, 2017 Eleventh IEEE/ACM International Symposium on Networks-on-Chip (NOCS).

A Case for Uni-directional Network Topologies in Large-Scale Clusters

Henri Casanova, Hideharu Amano, Hiroki Matsutani, 2017, 2017 IEEE International Conference on Cluster Computing (CLUSTER).

Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks

Hideharu Amano, Koji Nakano, Hiroki Matsutani, 2017, 2017 46th International Conference on Parallel Processing (ICPP).

A Novel Channel Assignment Method to Ensure Deadlock-Freedom for Deterministic Routing

Hideharu Amano, Ryuta Kawano, Hiroki Matsutani, 2017, IEICE Trans. Inf. Syst..

LOREN: A Scalable Routing Method for Layout-Conscious Random Topologies

Hideharu Amano, Ryuta Kawano, Hiroki Matsutani, 2016, 2016 Fourth International Symposium on Computing and Networking (CANDAR).

GPU-Accelerated Language and Communication Support by FPGA

Taisuke Boku, Hideharu Amano, Toshihiro Hanawa, 2018, Advanced Software Technologies for Post-Peta Scale Computing.

Efficient FPGA Implementation of Amoeba-inspired SAT Solver with Feedback and Bounceback Control: Harnessing Variable-Level Parallelism for Large-Scale Problem Solving in Edge Computing

H. Amano, 2023, HEART.

Automatic Pipeline Construction Focused on Similarity of Rate Law Functions for an FPGA-based Biochemical Simulator

Yuichiro Shibata, Kiyoshi Oguri, Hideharu Amano, 2010, IPSJ Trans. Syst. LSI Des. Methodol..

DIPROS - A DISTRIBUTED PROCESSING SYSTEM FOR NDL ON (SM)**2-II.

Taisuke Boku, Hideharu Amano, Tomohiro Kudoh, 1987 .

NCC: A concurrent description language for scientific calculation on multiprocessors

Taisuke Boku, Hideharu Amano, Tomohiro Kudoh, 1991, Systems and Computers in Japan.

High-Bandwidth Low-Latency Approximate Interconnection Networks

Henri Casanova, Hideharu Amano, Hiroki Matsutani, 2017, 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA).

Optical network technologies for HPC: computer-architects point of view

Hideharu Amano, Shu Namiki, Tomohiro Kudoh, 2016, IEICE Electron. Express.

Exploiting temporal parallelism in particle-based incompressive fluid simulation on FPGA

H. Amano, K. Kubota, Takaaki Miyajima, 2020, 2020 Eighth International Symposium on Computing and Networking (CANDAR).

Traffic-Independent Multi-Path Routing for High-Throughput Data Center Networks

Ryuta Kawano, Hideharu Amano, Michihiro Koibuchi, 2020, IEICE Trans. Inf. Syst..

Three-Dimensional Layout of On-Chip Tree-Based Networks

Hideharu Amano, D. Frank Hsu, Hiroki Matsutani, 2008, 2008 International Symposium on Parallel Architectures, Algorithms, and Networks (i-span 2008).

Tightly-Coupled Multi-Layer Topologies for 3-D NoCs

Hideharu Amano, Hiroki Matsutani, Michihiro Koibuchi, 2007, 2007 International Conference on Parallel Processing (ICPP 2007).

Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network

Hideharu Amano, Hiroki Matsutani, Michihiro Koibuchi, 2007, IEEE Transactions on Parallel and Distributed Systems.

Hierarchical multistage interconnection network R-Clos

Hideharu Amano, Keisuke Iwai, Tomohiro Morimura, 2006 .

Folded Fat H-Tree: An Interconnection Topology for Dynamically Reconfigurable Processor Array

Hideharu Amano, Yutaka Yamada, Katsunobu Nishimura, 2004, EUC.

Exploiting memory hierarchy for a Computational Fluid Dynamics accelerator on FPGAs

Hideharu Amano, Naoyuki Fujita, Yasunori Osana, 2008, 2008 International Conference on Field-Programmable Technology.

Mapping-Aware Kernel Partitioning Method for CGRAs Assisted by Deep Learning

Hideharu Amano, Takuya Kojima, Ayaka Ohwada, 2022, IEEE Transactions on Parallel and Distributed Systems.

Reducing the Configuration Loading Time of a Coarse Grain Multicontext Reconfigurable Device

Hideharu Amano, Kenichiro Anjo, Toshiro Kitaoka, 2003, FPL.

AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation

Hideharu Amano, Hiroki Matsutani, Michihiro Koibuchi, 2018, 2018 Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS).

ReCSiP: a reconfigurable cell simulation platform: accelerating biological applications with FPGA

H. Amano, Yasunori Osana, T. Fukushima, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

Overview of the JUMP-1, an MPP prototype for general-purpose parallel computations

Hiroshi Nakashima, Hideharu Amano, Hideo Matsuda, 1994, Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN).

The MDX (Multi-Dimensional X'bar): A Class of Networks for Large Scale Multiprocessors (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing)

Taisuke Boku, Hideharu Amano, Atsushi Murata, 1996 .