Chieh-Pu Lo

发表

A ReRAM-Based Nonvolatile Flip-Flop With Self-Write-Termination Scheme for Frequent-OFF Fast-Wake-Up Nonvolatile Processors

Meng-Fan Chang, Qi Wei, Huazhong Yang, 2017, IEEE Journal of Solid-State Circuits.

Embedded 2Mb ReRAM macro with 2.6ns read access time using dynamic-trip-point-mismatch sampling current-mode sense amplifier for IoE applications

Meng-Fan Chang, Yu-Der Chih, Ya-Chin King, 2017, 2017 Symposium on VLSI Circuits.

4.7 A 65nm ReRAM-enabled nonvolatile processor with 6× reduction in restore time and 4× higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic

Yu Wang, Meng-Fan Chang, Qi Wei, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

A 22-nm 1-Mb 1024-b Read Data-Protected STT-MRAM Macro With Near-Memory Shift-and-Rotate Functionality and 42.6-GB/s Read Bandwidth for Security-Aware Mobile Device

Yen-Cheng Chiu, Yu-Der Chih, Cheng-Xin Xue, 2021, IEEE Journal of Solid-State Circuits.

A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving $> 4\times $ Faster Clock Frequency and $> 6\times $ Higher Restore Speed

Kang L. Wang, Y. King, C. Lin, 2017, IEEE Journal of Solid-State Circuits.

An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications

Hidehiro Fujiwara, Tan-Li Chou, Yu-Der Chih, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

7.4 A 256b-wordlength ReRAM-based TCAM with 1ns search-time and 14× improvement in wordlength-energyefficiency-density product using 2.5T1R cell

Meng-Fan Chang, Tien-Fu Chen, Ya-Chin King, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

A Reflow-capable, Embedded 8Mb STT-MRAM Macro with 9nS Read Access Time in 16nm FinFET Logic CMOS Process

Y. Chih, Chieh-Pu Lo, H. Chuang, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

A ReRAM-based single-NVM nonvolatile flip-flop with reduced stress-time and write-power against wide distribution in write-time by using self-write-termination scheme for nonvolatile processors in IoT era

Meng-Fan Chang, Huazhong Yang, Yongpan Liu, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

A 22nm 4Mb STT-MRAM Data-Encrypted Near-Memory Computation Macro with a 192GB/s Read-and-Decryption Bandwidth and 25.1-55.1TOPS/W 8b MAC for AI Operations

Y. Chih, C. Lo, Chieh-Pu Lo, 2022, 2022 IEEE International Solid- State Circuits Conference (ISSCC).

33.1 A 16nm 32Mb Embedded STT-MRAM with a 6ns Read-Access Time, a 1M-Cycle Write Endurance, 20-Year Retention at 150°C and MTJ-OTP Solutions for Magnetic Immunity

Y. Chih, C. Kuo, Yih Wang, 2023, 2023 IEEE International Solid- State Circuits Conference (ISSCC).

A 462GOPs/J RRAM-based nonvolatile intelligent processor for energy harvesting IoE system featuring nonvolatile logics and processing-in-memory

Meng-Fan Chang, Huazhong Yang, Yuan Xie, 2017, 2017 Symposium on VLSI Technology.

13.3 A 22nm 32Mb Embedded STT-MRAM with 10ns Read Speed, 1M Cycle Write Endurance, 10 Years Retention at 150°C and High Immunity to Magnetic Field Interference

Yu-Lin Chen, Harry Chuang, Yu-Der Chih, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

A CMOS-integrated spintronic compute-in-memory macro for secure AI edge devices

Y. Chih, C. Lo, Chieh-Pu Lo, 2023, Nature Electronics.