Jinyoung Kim

An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme

Jin-Young Kim, Changhyun Kim, Hwan-Wook Park, 2006, IEEE Journal of Solid-State Circuits.

SCR-based ESD protection for high bandwidth DRAMs

Ki-Whan Song, Yeong-Taek Lee, Changhyun Kim, 2007, 2007 IEEE Asian Solid-State Circuits Conference.

A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth

Qi Wang, Jaewhan Kim, Jinyoung Kim, 2012, 2012 IEEE International Solid-State Circuits Conference.

A 58nm 1.8V 1Gb PRAM with 6.4MB/s program BW

Ki-Whan Song, Young-Hyun Jun, Jaewhan Kim, 2011, 2011 IEEE International Solid-State Circuits Conference.

A 64Mpixel CMOS Image Sensor with $0.50 \mu\mathrm{m}$ Unit Pixels Separated by Front Deep-Trench Isolation

Jinyoung Kim, Beomsuk Lee, Sungbong Park, 2022, IEEE International Solid-State Circuits Conference.

7.9 1/2.74-inch 32Mpixel-Prototype CMOS Image Sensor with 0.64μ m Unit Pixels Separated by Full-Depth Deep-Trench Isolation

Ho-Kyu Kang, Jinyoung Kim, H. Ji, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

Novel Deep Trench Buried-Body-Contact (DBBC) of 4F2 cell for sub 30nm DRAM technology

Chilhee Chung, Jinyoung Kim, Daeik Kim, 2012, 2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC).

A 31 ns Random Cycle VCAT-Based 4F $^{2}$ DRAM With Manufacturability and Enhanced Cell Efficiency

Ki-Whan Song, Young-Hyun Jun, Jinyoung Kim, 2010, IEEE Journal of Solid-State Circuits.