Abhijit Ghosh

发表

Methodology for hardware/software co-verification in C/C++ (short paper)

Abhijit Ghosh, Luc Séméria, L. Semeria, 2000, ASP-DAC '00.

An observability-based code coverage metric for functional simulation

K. Keutzer, S. Devadas, Abhijit Ghosh, 1996, Proceedings of International Conference on Computer Aided Design.

Probabilistic construction and manipulation of Free Boolean Diagrams

Srinivas Devadas, Abhijit Ghosh, Amelia Shen, 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

Retiming sequential circuits for low power

S. Devadas, Abhijit Ghosh, J. Monteiro, 1993, ICCAD '93.

Sequential test generation at the register-transfer and logic levels

A. Newton, S. Devadas, Abhijit Ghosh, 1990, 27th ACM/IEEE Design Automation Conference.

Modeling failure types and failure times of turning and boring machine systems

Abhijit Ghosh, Sujit Kumar Majumdar, Abhijit Ghosh, 2010 .

Estimation of average switching activity in combinational and sequential circuits

Kurt Keutzer, Srinivas Devadas, Jacob K. White, 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

YAML: a tool for hardware design visualization and capture

Rajesh K. Gupta, S. Liao, Abhijit Ghosh, 2000, Proceedings 13th International Symposium on System Synthesis.

Methodology for hardware/software co-verification in C/C++

Abhijit Ghosh, Luc Séméria, L. Semeria, 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

Implicit state transition graphs: applications to sequential logic synthesis and test

Srinivas Devadas, A. Richard Newton, Abhijit Ghosh, 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

Modeling blast furnace productivity using support vector machines

Abhijit Ghosh, Sujit K. Majumdar, Abhijit Ghosh, 2011 .

A unique approach for Market Basket Analysis under the framework of Probability Based

Anupam Mondal, Abhijit Ghosh, Abhijit Sarkar, 2014 .

Recent progress in synthesis for testability

Kurt Keutzer, Srinivas Devadas, Abhijit Ghosh, 1991, Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's.

Retiming sequential circuits for low power

Srinivas Devadas, José Monteiro, Abhijit Ghosh, 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

Hierarchical scheduling in high level synthesis using resource sharing across nested loops

Ranga Vemuri, Abhijit Ghosh, Sandeep K. Lodha, 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

Sequential logic optimization for low power using input-disabling precomputation architectures

José C. Monteiro, Srinivas Devadas, Abhijit Ghosh, 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Precomputation-based Sequential Logic Optimization For Low Power

A. Ghosh, M. Alidina, J. Monteiro, 1994, IEEE/ACM International Conference on Computer-Aided Design.

Test generation and verification for highly sequential circuits

Srinivas Devadas, A. Richard Newton, Abhijit Ghosh, 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Sequential test generation and synthesis for testability at the register-transfer and logic levels

Srinivas Devadas, A. Richard Newton, Abhijit Ghosh, 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Sequential logic synthesis for testability using register-transfer level descriptions

Srinivas Devadas, A. Richard Newton, Abhijit Ghosh, 1990, Proceedings. International Test Conference 1990.

Different Intrusion and Its Detection of Wireless Sensor Network: a Review

Abhijit Ghosh, Piyu Sarcar, Rimpi Datta, 2019, INTERNATIONAL JOURNAL OF ELECTRONICS & COMMUNICATION ENGINEERING & TECHNOLOGY .

On average power dissipation and random pattern testability of CMOS combinational logic networks

K. Keutzer, S. Devadas, Abhijit Ghosh, 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

Test generation for highly sequential circuits

Srinivas Devadas, A. Richard Newton, Abhijit Ghosh, 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

Boolean satisfiability and equivalence checking using general binary decision diagrams

Srinivas Devadas, Abhijit Ghosh, Pranav Ashar, 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

Probabilistic manipulation of Boolean functions using free Boolean diagrams

Srinivas Devadas, Abhijit Ghosh, Amelia Shen, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..