S. Fujita

发表

Monolithic integration of CMOS VLSI and CNT for hybrid nanotechnology applications

H. Wong, D. Akinwande, S. Yasuda, 2008, ESSDERC 2008 - 38th European Solid-State Device Research Conference.

Impact of ultra low power and fast write operation of advanced perpendicular MTJ on power reduction for high-performance mobile CPU

N. Shimomura, E. Kitagawa, H. Yoda, 2012, 2012 International Electron Devices Meeting.

Spin-transfer torque magnetoresistive random-access memory technologies for normally off computing (invited)

S. Yuasa, K. Ando, Y. Nakatani, 2014 .

Impact of a Process Variation on Nanowire and Nanotube Device Performance

H. Wong, Y. Nishi, B. Paul, 2007, IEEE Transactions on Electron Devices.

A 1 GHz integrated circuit with carbon nanotube interconnects and silicon transistors.

Shinobu Fujita, Shinichi Yasuda, H. Wong, 2008, Nano letters.

Hierarchical Nonvolatile Memory with Perpendicular Magnetic Tunnel Junctions for Normally-Off Computing

Kumiko Nomura, Shinobu Fujita, Hiroaki Yoda, 2010 .

Low-Power and High-Speed Nonvolatile FPGA by Adjacent Integration of MONOS/Logic and Novel Programming Scheme

Shinobu Fujita, Mari Matsumoto, Masato Oda, 2014 .

Sub-ns Delay Through Multi-Wall Carbon Nanotube Local Interconnects in a CMOS Integrated Circuit

H. Wong, S. Yasuda, B. Paul, 2008, 2008 International Interconnect Technology Conference.

An Analytical Compact Circuit Model for Nanowire FET

Y. Nishi, S. Fujita, T.H. Lee, 2007, IEEE Transactions on Electron Devices.

A Circuit Compatible Analytical Device Model for Nanowire FET Considering Ballistic and Drift-Diffusion Transport

Y. Nishi, T. Lee, R. Tu, 2007 .

Fully Integrated Graphene and Carbon Nanotube Interconnects for Gigahertz High-Speed CMOS Electronics

Jing Kong, Kyeong-Jae Lee, H. Wong, 2010, IEEE Transactions on Electron Devices.

Fault-Tolerant Circuit for Carbon Nanotube Transistors with Si-CMOS Hybrid Circuitry

H. Wong, D. Akinwande, S. Yasuda, 2008, 2008 8th IEEE Conference on Nanotechnology.

Impact of geometry-dependent parasitic capacitances on the performance of CNFET circuits

B. Paul, S. Fujita, M. Okajima, 2006, IEEE Electron Device Letters.

The effect of local structure and non-uniformity on decoherence-free states of charge qubits

S. Fujita, T. Tanamoto, 2005, quant-ph/0512244.

The progresses of MRAM as a memory to save energy consumption and its potential for further reduction

N. Shimomura, M. Amano, E. Kitagawa, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

The effect of local structure and non-uniformity on decoherence-free states of charge qubits

S. Fujita, T. Tanamoto, 2005, quant-ph/0512244.

Numerical Simulations of Automatic Change of Threshold Voltage Shift in SRAM With Double-Floating-Gate Structures

S. Fujita, K. Tatsumura, A. Kinoshita, 2012, IEEE Transactions on Electron Devices.

Non-volatile Memories

S. Fujita, Y. Fujimori, K. Ando, 2017 .

Noise characteristics of the Fano effect and the Fano–Kondo effect in triple quantum dots

S. Fujita, Y. Nishi, T. Tanamoto, 2009, Journal of physics. Condensed matter : an Institute of Physics journal.

Monolithic Integration of CMOS VLSI and Carbon Nanotubes for Hybrid Nanotechnology Applications

S. Fujita, D. Akinwande, S. Yasuda, 2008, IEEE Transactions on Nanotechnology.

The Effect of Side Traps on Ballistic Transistor in Kondo Regime

K. Uchida, S. Fujita, T. Tanamoto, 2006, cond-mat/0608011.

A 250-MHz 256b-I/O 1-Mb STT-MRAM with advanced perpendicular MTJ based dual cell for nonvolatile magnetic caches to reduce active power of processors

Saori Kashiwada, Hiroki Noguchi, Shinobu Fujita, 2013, 2013 Symposium on VLSI Circuits.

Single-electron random-number generator (RNG) for highly secure ubiquitous computing applications

K. Uchida, S. Fujita, T. Tanamoto, 2002, Digest. International Electron Devices Meeting,.

Ultra-high-efficient Writing in Voltage-Control Spintronics Memory(VoCSM); the Most Promising Embedded Memory for Deep Learning

M. Shimizu, H. Yoda, N. Shimomura, 2018, 2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM).

The Prospect and Challenges of CNFET Based Circuits: A Physical Insight

Bipul C. Paul, Shinobu Fujita, Masaki Okajima, 2010 .

Modeling and analysis of circuit performance of ballistic CNFET

Shinobu Fujita, Bipul Chandra Paul, Thomas Lee, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

Producing cluster states in charge qubits and flux qubits.

F. Nori, S. Fujita, Xuedong Hu, 2006, Physical review letters.

7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture

Satoshi Takaya, Hiroki Noguchi, Shinobu Fujita, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

Novel voltage controlled MRAM (VCM) with fast read/write circuits for ultra large last level cache

Yoshishige Suzuki, Hiroki Noguchi, Shinobu Fujita, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Ultra low power processor using perpendicular-STT-MRAM/SRAM based hybrid cache toward next generation normally-off computers

Kumiko Nomura, Shinobu Fujita, Hiroaki Yoda, 2012 .

Low-power cache memory with state-of-the-art STT-MRAM for high-performance processors

Kumiko Nomura, Hiroshi Nakamura, Shinobu Miwa, 2015, 2015 International SoC Design Conference (ISOCC).

Novel Nonvolatile L1/L2/L3 Cache Memory Hierarchy Using Nonvolatile-SRAM With Voltage-Induced Magnetization Switching and Ultra Low-Write-Energy MTJ

Shinobu Fujita, H. Noguchi, K. Abe, 2013, IEEE Transactions on Magnetics.

Progress of STT-MRAM technology and the effect on normally-off computing systems

H. Noguchi, K. Abe, S. Fujita, 2012, 2012 International Electron Devices Meeting.

Research and Development of Normally-Off Computing—NEDO Project

Shintaro Izumi, Masanori Hayashikoshi, Hiroshi Nakamura, 2017 .

A low-overhead fault tolerance scheme for TSV-based 3D network on chip links

Luca Benini, Igor Loi, Shinobu Fujita, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

1200μm2 Physical Random-Number Generators Based on SiN MOSFET for Secure Smart-Card Application

Shinobu Fujita, Tetsufumi Tanamoto, Mari Matsumoto, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

Physical random number generator based on MOS structure after soft breakdown

R. Ohba, K. Uchida, S. Fujita, 2004, IEEE Journal of Solid-State Circuits.

High-speed graphene interconnects monolithically integrated with CMOS ring oscillators operating at 1.3GHz

Jing Kong, H.-S. Philip Wong, Shinobu Fujita, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Future prospects of MRAM technologies

Y. Suzuki, H. Noguchi, S. Fujita, 2013, 2013 IEEE International Electron Devices Meeting.

Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU

Hiroki Noguchi, Shinobu Fujita, Junichi Ito, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

10 nm bulk-planar SONOS-type memory with double tunnel junction and sub-10 nm scaling utilizing source to drain direct tunnel sub-threshold

S. Fujita, Y. Mitani, R. Ohba, 2008, 2008 IEEE International Electron Devices Meeting.

7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme

Hiroshi Nakamura, Satoshi Takaya, Hiroki Noguchi, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

Advanced Perpendicular STT-MRAM Technologies for Power Reduction of High-performance Processors

Hiroki Noguchi, Shinobu Fujita, Hiroaki Yoda, 2015 .

Roles of Non-Volatile Devices in Future Computer Systems: Normally-Off Computers

Shinobu Fujita, Hiroaki Yoda, Sumio Ikegawa, 2012 .

Circuit and systems based on advanced MRAM for near future computing applications

Shinobu Fujita, Kazutaka Ikegami, Susumu Takeda, 2019, 2019 Symposium on VLSI Technology.

ROM based logic (RBL) design: High-performance and low-power adders

Shinobu Fujita, Bipul Chandra Paul, Masaki Okajima, 2008, 2008 IEEE International Symposium on Circuits and Systems.

Designing Nonvolatile Reconfigurable Switch-based FPGA through Overall Circuit Performance Evaluation

Kumiko Nomura, Shinobu Fujita, Keiko Abe, 2012, 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum.

Normally-off type nonvolatile static random access memory with perpendicular spin torque transfer-magnetic random access memory cells and smallest number of transistors

S. Fujita, C. Tanaka, K. Nomura, 2014 .

35 nm floating gate planar MOSFET memory using double junction tunneling

N. Sugiyama, S. Fujita, Y. Mitani, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..