C. Duvvury

发表

The impact of technology scaling on ESD robustness and protection circuit design

C. Duvvury, A. Amerasekera, A. Amerasekera, 1995 .

ESD phenomena in graded junction devices

C. Duvvury, R. Rountree, H. Stiegler, 1989 .

Achieving uniform nMOS device power distribution for sub-micron ESD reliability

C. Duvvury, C. Diaz, T. Haddock, 1992, 1992 International Technical Digest on Electron Devices Meeting.

ESD Protection Reliability in 1μM CMOS Technologies

C. Duvvury, R. Rountree, R. A. McPhee, 1986, 24th International Reliability Physics Symposium.

ESD in silicon integrated circuits

E. A. Amerasekera, C. Duvvury, 1995 .

Analysis of ESD protection components in 65nm CMOS technology: Scaling perspective and impact on ESD design window

C. Duvvury, G. Boselli, J. Rodriguez, 2005, 2005 Electrical Overstress/Electrostatic Discharge Symposium.

Embedded Tutorial: Silicon Technology Impact on ESD Qualification

C. Duvvury, 2013, 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems.

Analysis of nonuniform ESD current distribution in deep submicron NMOS transistors

Kaustav Banerjee, Charvaka Duvvury, Robert W. Dutton, 2002 .

State-of-the-art issues for technology and circuit design of ESD protection in CMOS ICs

Charvaka Duvvury, Ajith Amerasekera, A. Amerasekera, 1996 .

Non-uniform bipolar conduction in single finger NMOS transistors and implications for deep submicron ESD design

Kaustav Banerjee, Robert W. Dutton, C. Duvvury, 2001, 2001 IEEE International Reliability Physics Symposium Proceedings. 39th Annual (Cat. No.00CH37167).

ESD Evaluation of the Emerging MuGFET Technology

W. Xiong, H. Gossner, T. Schulz, 2007, IEEE Transactions on Device and Materials Reliability.

ESD evaluation of the emerging MuGFET technology

A. Marshall, C. Duvvury, C.R. Cleavelin, 2005, 2005 Electrical Overstress/Electrostatic Discharge Symposium.

Unique ESD Failure Mechanism in a MuGFET Technology

C. Duvvury, H. Gossner, T. Schulz, 2006, 2006 International Electron Devices Meeting.

Modeling of temperature dependent contact resistance for analysis of ESD reliability

R. Dutton, K. Banerjee, C. Duvvury, 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..

Substrate pump NMOS for ESD protection applications

C. Duvvury, A. Amerasekera, V. Gupta, 2000, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476).

ESD Failure Caused by Localized Charge Injection

H. Kunz, R. Dutton, C. Duvvury, 2004 .

An Insight Into ESD Behavior of Nanometer-Scale Drain Extended NMOS (DeNMOS) Devices: Part II (Two-Dimensional Study-Biasing & Comparison With NMOS)

M. Shrivastava, H. Gossner, C. Duvvury, 2011, IEEE Transactions on Electron Devices.

Hot-Carrier Degradation Effects for DRAM Circuits

C. Duvvury, S. Aur, 1992 .

Reliability design of p/sup +/-pocket implant LDD transistors

Charvaka Duvvury, C. Duvvury, T. Holloway, 1990, International Technical Digest on Electron Devices.

Series resistance modeling for optimum design of LDD transistors

C. Duvvury, D. Baglee, M. Duane, 1983, 1983 International Electron Devices Meeting.

System Level ESD: Part II: Implementation of Effective ESD Robust Designs: White Paper 3

Jeffrey Dunnihoo, Charvaka Duvvury, Wolfgang Reinprecht, 2019 .

Excitation characteristics of the IR luminescence in CU2O

C. Duvvury, F. Weichman, D. Kenway, 1975 .

Evidence of a competitive phenomenon between the 0.72 μm and 0.93 μm luminescences of Cu2O

C. Duvvury, F. Weichman, D. Kenway, 1978 .

Temperature-Dependent Electrical Resistivity of Potassium below 2 K

C. Duvvury, J. Rowlands, S. B. Woods, 1978 .

Electrical overstress and electrostatic discharge

Sung-Mo Kang, C. Duvvury, C. Diaz, 1995 .

FinFET current mirror design and evaluation

G. Knoblinger, A. Marshall, C. Duvvury, 2005, 2005 IEEE Dallas/CAS Workshop on Architecture, Circuits and Implementtation of SOCs.

Discontinuing Use of the Machine Model for Device ESD Qualification

R. Ashton, H. Gossner, C. Duvvury, 2013 .

Dynamic gate coupling of NMOS for efficient output ESD protection

C. Duvvury, C. Diaz, C. Duvvury, 1992, 30th Annual Proceedings Reliability Physics 1992.

CDM peak current variations and impact upon CDM performance thresholds

C. Duvvury, S. Marum, J. Schichl, 2007, 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).

An Insight Into the ESD Behavior of the Nanometer-Scale Drain-Extended NMOS Device—Part I: Turn-On Behavior of the Parasitic Bipolar

H Gossner, M Shrivastava, M. Shrivastava, 2011, IEEE Transactions on Electron Devices.

A guide to short-channel effects in MOSFETs

C. Duvvury, C. Duvvury, 1986, IEEE Circuits and Devices Magazine.

Latch-up in 65nm CMOS technology: a scaling perspective

C. Duvvury, V. Reddy, G. Boselli, 2005, 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual..

An analytical method for determining intrinsic drain/source resistance of lightly doped drain (LDD) devices

A. Hyslop, C. Duvvury, D. Baglee, 1984 .

EOS/ESD reliability of deep sub-micron NMOS protection devices

Sung-Mo Kang, S. Ramaswamy, C. Duvvury, 1995, Proceedings of 1995 IEEE International Reliability Physics Symposium.

Setting the trap for hot carriers [MOS VLSI]

C. Duvvury, S. Aur, W.R. Hunter, 1995, IEEE Circuits and Devices Magazine.

Impact of Hot Carriers on Dram Circuits

C. Duvvury, H. Kitagawa, D. Redwine, 1987, 25th International Reliability Physics Symposium.

Characterization and Optimization of Sub-32-nm FinFET Devices for ESD Applications

R. Rooyackers, C. Duvvury, N. Collaert, 2008, IEEE Transactions on Electron Devices.