A. Orailoglu

发表

Coactive scheduling and checkpoint determination during high level synthesis of self-recovering microarchitectures

Ramesh Karri, Alex Orailoglu, R. Karri, 1994, IEEE Trans. Very Large Scale Integr. Syst..

Test application time and volume compression through seed overlapping

Wenjing Rao, Alex Orailoglu, Ismet Bayraktaroglu, 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

Frequency-domain Compatibility In Digital Filter Bist

A. Orailoglu, L. Goodby, 1997, Proceedings of the 34th Design Automation Conference.

Test of Mismatch

A. Orailoglu, R. Topaloglu, 2022 .

-1 - " Property-based Rtl Test Justification and Propagation Analysis " * * This Work Is Supported Partially through a Research Grant from Intel Corporation

A. Orailoglu, Y. Makris, 1999 .

Principles of Computer Architecture – CSE 240A

A. Orailoglu, Chengmo Yang, 2008 .

A Community Review of Logic Locking: Reﬂections, Benchmarking, and Outlook

Vivek V. Menon, Md. Moshiur Rahman, Ankur Srivastava, 2022 .

Pseudorandom-pattern test resistance in high-performance DSP datapaths

A. Orailoglu, L. Goodby, 1996, 33rd Design Automation Conference Proceedings, 1996.

A Design Methodology For The High-level Synthesis Of Fault-tolerant Asics

Ramesh Karri, Alex Orailoglu, R. Karri, 1992, Workshop on VLSI Signal Processing.

Design Space Exploration for Aggressive Test Cost Reduction in Circular Scan Architectures

A. Orailoglu, B. Arslan, 2004 .

Partial core encryption for performance-efficient test of SOCs

O. Sinanoglu, A. Orailoglu, 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

Debugging Methods Through Identification of Appropriate Functions for Internal Gates

A. Orailoglu, L. Silveira, M. Margala, 2018 .

Fault tolerant quantum cellular array (QCA) design using triple modular redundancy with shifted operands

Tongquan Wei, Ramesh Karri, Kaijie Wu, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Fault tolerant nanoelectronic processor architectures

Ramesh Karri, Wenjing Rao, Alex Orailoglu, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

ALPS: Algorithm for pipelined data path synthsis

Ramesh Karri, Alex Orailoglu, R. Karri, 1991 .

Simulated annealing based yield enhancement of layouts

Ramesh Karri, Alex Orailoglu, R. Karri, 1994, Proceedings of 4th Great Lakes Symposium on VLSI.

CUSTOMIZABLE EMBEDDED SYSTEM ARCHITECTURES

A. Orailoglu, P. Petrov, 2007 .

Can Defect-Tolerant Chips Better Meet the Quality Challenge?

Wojciech Maly, Alex Orailoglu, Michael Nicolaidis, 1996, VTS.

On mismatch in the deep sub-micron era - from physics to circuits

A. Orailoglu, R. Topaloglu, 2004 .

Detecting Gas Vapor Leaks Using Uncalibrated Sensors

A. Enis Çetin, Sule Ozev, Alex Orailoglu, 2019, IEEE Access.

Autonomous yet deterministic test of SOC cores

Ozgur Sinanoglu, Alex Orailoglu, O. Sinanoglu, 2004, 2004 International Conferce on Test.

Unleashing the Potential of Sparse DNNs Through Synergistic Hardware-Sparsity Co-Design

A. Orailoglu, Elbruz Ozen, 2023, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

SNR: Squeezing Numerical Range Defuses Bit Error Vulnerability Surface in Deep Neural Networks

Alex Orailoglu, Elbruz Ozen, A. Orailoglu, 2021, ACM Trans. Embed. Comput. Syst..

Low-Cost Error Detection in Deep Neural Network Accelerators with Linear Algorithmic Checksums

Alex Orailoglu, Elbruz Ozen, A. Orailoglu, 2021, J. Electron. Test..

Just Say Zero: Containing Critical Bit-Error Propagation in Deep Neural Networks With Anomalous Feature Suppression

Alex Orailoglu, Elbruz Ozen, A. Orailoglu, 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

Boosting Bit-Error Resilience of DNN Accelerators Through Median Feature Selection

Alex Orailoglu, Elbruz Ozen, A. Orailoglu, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Concurrent Monitoring of Operational Health in Neural Networks Through Balanced Output Partitions

Alex Orailoglu, Elbruz Ozen, A. Orailoglu, 2020, 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC).

Architecting Decentralization and Customizability in DNN Accelerators for Hardware Defect Adaptation

A. Orailoglu, Elbruz Ozen, 2022, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Shaping Resilient AI Hardware Through DNN Computational Feature Exploitation

A. Orailoglu, Elbruz Ozen, 2023, IEEE Design & Test.

Evolving Complementary Sparsity Patterns for Hardware-Friendly Inference of Sparse DNNs

Alex Orailoglu, Elbruz Ozen, A. Orailoglu, 2021, 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

A. Orailoglu, Elbruz Ozen, 2020, ECML/PKDD.

Sanity-Check: Boosting the Reliability of Safety-Critical Deep Neural Network Applications

Alex Orailoglu, Elbruz Ozen, A. Orailoglu, 2019, 2019 IEEE 28th Asian Test Symposium (ATS).

Tackling Resource Variations Through Adaptive Multicore Execution Frameworks

Alex Orailoglu, Chengmo Yang, A. Orailoglu, 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Frugal but flexible multicore topologies in support of resource variation-driven adaptivity

Alex Orailoglu, Chengmo Yang, A. Orailoglu, 2011, 2011 Design, Automation & Test in Europe.

Light-weight synchronization for inter-processor communication acceleration on embedded MPSoCs

Alex Orailoglu, Chengmo Yang, A. Orailoglu, 2007, CASES '07.

Minming Li, Chun Jason Xue, Alex Orailoglu, 2013, TECS.

Minming Li, Chun Jason Xue, Alex Orailoglu, 2011, 2011 Design, Automation & Test in Europe.

Scan Power Reduction for Linear Test Compression Schemes Through Seed Selection

Mingjing Chen, Alex Orailoglu, A. Orailoglu, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Scan power reduction in linear test data compression scheme

Mingjing Chen, Alex Orailoglu, A. Orailoglu, 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

Design of concurrent test Hardware for Linear analog circuits with constrained hardware overhead

Sule Ozev, Alex Orailoglu, A. Orailoglu, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

On the identification of modular test requirements for low cost hierarchical test path construction

Yiorgos Makris, Alex Orailoglu, A. Orailoglu, 2007, Integr..

Piercing Logic Locking Keys through Redundancy Identification

Alex Orailoglu, Leon Li, A. Orailoglu, 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Joint Profit and Process Variation Aware High Level Synthesis With Speed Binning

Chun Jason Xue, Alex Orailoglu, Mengying Zhao, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A module diagnosis and design-for-debug methodology based on hierarchical test paths

Yiorgos Makris, Alex Orailoglu, A. Orailoglu, 1999, Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99).

Flip-Flop Hardening and Selection for Soft Error and Delay Fault Resilience

Mingjing Chen, Alex Orailoglu, A. Orailoglu, 2009, 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Improving Circuit Robustness with Cost-Effective Soft-Error-Tolerant Sequential Elements

Mingjing Chen, A. Orailoglu, A. Orailoglu, 2007, 16th Asian Test Symposium (ATS 2007).

Towards fault tolerant parallel prefix adders in nanoelectronic systems

Wenjing Rao, Alex Orailoglu, A. Orailoglu, 2008, 2008 Design, Automation and Test in Europe.

End-to-end testability analysis and DfT insertion for mixed-signal paths

Sule Ozev, Alex Orailoglu, A. Orailoglu, 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

Microarchitectural synthesis of performance-constrained, low-power VLSI designs

Alex Orailoglu, Paul M. Chau, Laurence Goodby, 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

Forward discrete probability propagation method for device performance characterization under process variations

Alex Orailoglu, Rasit Onur Topaloglu, A. Orailoglu, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

On mismatch in the deep sub-micron era-from physics to circuits

Alex Orailoglu, Rasit O. Topaloglu, A. Orailoglu, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2003, Newport Beach, CA, USA, October 1-3, 2003

Alex Orailoglu, Yukihiro Nakamura, Pai H. Chou, 2003, International Conference on Hardware/Software Codesign and System Synthesis.

User interface issues in a high level test synthesis environment

Ian G. Harris, A. Orailoglu, A. Orailoglu, 1997, Proceedings of 40th Midwest Symposium on Circuits and Systems. Dedicated to the Memory of Professor Mac Van Valkenburg.

Microarchitectural synthesis for rapid BIST testing

Alex Orailoglu, A. Orailoglu, 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Automatic Synthesis of Self-Recovering VLSI Systems

Ramesh Karri, Alex Orailoglu, R. Karri, 1996, IEEE Trans. Computers.

Metric-based transformations for self testable VLSI designs with high test concurrency

Alex Orailoglu, Mahsa Vahidi, A. Orailoglu, 1995, Proceedings of EURO-DAC. European Design Automation Conference.

Testability metrics for synthesis of self-testable designs and effective test plans

Alex Orailoglu, Mahsa Vahidi, A. Orailoglu, 1995, Proceedings 13th IEEE VLSI Test Symposium.

Integrating binding constraints in the synthesis of area-efficient self-recovering microarchitectures

Alex Orailoglu, Karin Högstedt, A. Orailoglu, 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

SYNCBIST: SYNthesis for concurrent built-in self-testability

Alex Orailoglu, Ian G. Harris, A. Orailoglu, 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

Optimal self-recovering microarchitecture synthesis

Ramesh Karri, Alex Orailoglu, R. Karri, 1993, FTCS-23 The Twenty-Third International Symposium on Fault-Tolerant Computing.

A framework for fault-tolerant microarchitecture synthesis

Ramesh Karri, A. Orailoglu, A. Orailoglu, 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

Intertwined scheduling, module selection and allocation in time-and-area

Ian G. Harris, Alex Orailoglu, A. Orailoglu, 1993, 1993 IEEE International Symposium on Circuits and Systems.

High-level synthesis of self-recovering microarchitectures

Ramesh Karri, Alex Orailoglu, R. Karri, 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

Pipeline data path synthesis of fault-tolerant microarchitectures

Ramesh Karri, Alex Orailoglu, A. Orailoglu, 1992, [1992] Proceedings of the 35th Midwest Symposium on Circuits and Systems.

Transformation-based high-level synthesis of fault-tolerant ASICs

Ramesh Karri, Alex Orailoglu, R. Karri, 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

High-level synthesis of fault-tolerant ASICs

Ramesh Karri, Alex Orailoglu, R. Karri, 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

Test volume and application time reduction through scan chain concealment

Alex Orailoglu, Ismet Bayraktaroglu, A. Orailoglu, 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

ALPS: an algorithm for pipeline data path synthesis

Ramesh Karri, Alex Orailoglu, R. Karri, 1991, MICRO 24.

AdaTrust: Combinational Hardware Trojan Detection Through Adaptive Test Pattern Construction

Alex Orailoglu, Chris Nigh, A. Orailoglu, 2021, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Power-Conscious Microprocessor-Based Testing of System-on-Chip(テスト,システム設計及び一般)

Fawnizu Azmadi Hussin, Hideo Fujiwara, Tomokazu Yoneda, 2006 .

Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking pdf

Hai Zhou, Franco Stellari, Ujjwal Guin, 2020, ArXiv.

Flow Graph Representation

Daniel Gajski, Alex Orailoglu, D. Gajski, 1986, 23rd ACM/IEEE Design Automation Conference.

Low-Cost Error Detection in Deep Neural Network Accelerators with Linear Algorithmic Checksums

A. Orailoglu, Elbruz Ozen, 2020, Journal of Electronic Testing.

Concurrent test for digital linear systems

Alex Orailoglu, Ismet Bayraktaroglu, A. Orailoglu, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Miss reduction in embedded processors through dynamic, power-friendly cache design

Alex Orailoglu, Garo Bournoutian, A. Orailoglu, 2008, 2008 45th ACM/IEEE Design Automation Conference.

On Diagnosis of Timing Failures in Scan Architecture

Mingjing Chen, Alex Orailoglu, A. Orailoglu, 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Diagnosing scan clock delay faults through statistical timing pruning

Mingjing Chen, Alex Orailoglu, A. Orailoglu, 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

Diagnosing scan chain timing faults through statistical feature analysis of scan images

Mingjing Chen, Alex Orailoglu, A. Orailoglu, 2011, 2011 Design, Automation & Test in Europe.

Decision tree based mismatch diagnosis in analog circuits

Mingjing Chen, Alex Orailoglu, Hosam Haggag, 2006, 24th IEEE VLSI Test Symposium.

JANUS-HD: Exploiting FSM Sequentiality and Synthesis Flexibility in Logic Obfuscation to Thwart SAT Attack While Offering Strong Corruption

A. Orailoglu, Leon Li, 2022, 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE).

JANUS: Boosting Logic Obfuscation Scope Through Reconfigurable FSM Synthesis

A. Orailoglu, Leon Li, Shuyi Ni, 2021, 2021 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

Power-Constrained SOC Test Schedules through Utilization of Functional Buses

Fawnizu Azmadi Hussin, Hideo Fujiwara, Alex Orailoglu, 2006, 2006 International Conference on Computer Design.

Compacting test responses for deeply embedded SoC cores

Ozgur Sinanoglu, Alex Orailoglu, O. Sinanoglu, 2003, IEEE Design & Test of Computers.

Mobile Ecosystem Driven Dynamic Pipeline Adaptation for Low Power

Alex Orailoglu, Garo Bournoutian, A. Orailoglu, 2015, ARCS.

Dynamic transient fault detection and recovery for embedded processor datapaths

Alex Orailoglu, Garo Bournoutian, A. Orailoglu, 2012, CODES+ISSS.

Towards Nanoelectronics Processor Architectures

Ramesh Karri, Wenjing Rao, Alex Orailoglu, 2007, J. Electron. Test..

Fault tolerant nanoelectronic processor architectures

Ramesh Karri, Wenjing Rao, A. Orailoglu, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Energy frugal tags in reprogrammable I-caches for application-specific embedded processors

Peter Petrov, Alex Orailoglu, A. Orailoglu, 2002, Proceedings of the Tenth International Symposium on Hardware/Software Codesign. CODES 2002 (IEEE Cat. No.02TH8627).

Towards no-cost adaptive MPSoC static schedules through exploitation of logical-to-physical core mapping latitude

Alex Orailoglu, Chengmo Yang, A. Orailoglu, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

Automated System-Level Test Development for Mixed-Signal Circuits

Sule Ozev, Alex Orailoglu, A. Orailoglu, 2003 .

Low-power instruction bus encoding for embedded processors

Peter Petrov, Alex Orailoglu, A. Orailoglu, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

On the relation between SAT and BDDs for equivalence checking

Rolf Drechsler, Alex Orailoglu, Sherief Reda, 2002, Proceedings International Symposium on Quality Electronic Design.

A unified transformational approach for reductions in fault vulnerability, power, and crosstalk noise and delay on processor buses

A. Orailoglu, R. Ayoub, A. Orailoglu, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Redundancy Attack: Breaking Logic Locking Through Oracleless Rationality Analysis

A. Orailoglu, Leon Li, 2023, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Power efficient branch prediction through early identification of branch addresses

Alex Orailoglu, Chengmo Yang, A. Orailoglu, 2006, CASES '06.

Filtering Global History: Power and Performance Efficient Branch Predictor

Alex Orailoglu, Raid Ayoub, A. Orailoglu, 2009, 2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors.