M. Yamaoka

发表

A 300-MHz 25-/spl mu/A/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor

Yasuhisa Shimazaki, Y. Shinozaki, Shigeru Shimada, 2004, IEEE Journal of Solid-State Circuits.

Voltage and temperature dependence of random telegraph noise in highly scaled HKMG ETSOI nFETs and its impact on logic delay uncertainty

D. Frank, D. Park, M. Yamaoka, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Impact of threshold voltage fluctuation due to random telegraph noise on scaled-down SRAM

M. Yamaoka, N. Tega, H. Miki, 2008, 2008 IEEE International Reliability Physics Symposium.

Understanding short-term BTI behavior through comprehensive observation of gate-voltage dependence of RTN in highly scaled high-κ / metal-gate pFETs

D. Frank, W. Haensch, M. Guillorn, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Outline of CMOS Annealing Machine

M. Yamaoka, 2020 .

Problem to be solved Combinatorial optimization problem Ising model Ising model ( hardware optimized ) Solution Modeling Conversion Embedding Ground-state search

M. Yamaoka, C. Yoshimura, M. Hayashi, 2016 .

A Fully-Connected Ising Model Embedding Method and Its Evaluation for CMOS Annealing Machines

Nozomu Togawa, Daisuke Oku, Kotaro Terada, 2019, IEICE Trans. Inf. Syst..

Binary optimization by momentum annealing.

Ken-ichi Kawarabayashi, Tomohiro Sonobe, Masanao Yamaoka, 2019, Physical review. E.

A 20k-Spin Ising Chip to Solve Combinatorial Optimization Problems With CMOS Annealing

Hiroyuki Mizuno, Masanao Yamaoka, Masato Hayashi, 2016, IEEE Journal of Solid-State Circuits.

Uncertain behaviours of integrated circuits improve computational performance

Ken-ichi Kawarabayashi, Hiroyuki Mizuno, Masanao Yamaoka, 2015, Scientific Reports.

Minor-embedding heuristics for large-scale annealing processors with sparse hardware graphs of up to 102,400 nodes pdf

Atsuyoshi Nakamura, Ichigaku Takigawa, Hiroshi Teramoto, 2020, Soft Computing.

Computing architecture to perform approximated simulated annealing for Ising models

Masanao Yamaoka, Masato Hayashi, Chihiro Yoshimura, 2016, 2016 IEEE International Conference on Rebooting Computing (ICRC).

Spatial computing architecture using randomness of memory cell stability under voltage control

Hiroyuki Mizuno, Masanao Yamaoka, Chihiro Yoshimura, 2013, 2013 European Conference on Circuit Theory and Design (ECCTD).

STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin–Spin Interactions

Shinya Takamaeda-Yamazaki, Masato Motomura, Hiroshi Teramoto, 2020, IEEE Journal of Solid-State Circuits.

7.3 STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions

Masato Motomura, Hiroshi Teramoto, Shinya Takamaeda-Yamazaki, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

2.6 A 2 ×30k-Spin Multichip Scalable Annealing Processor Based on a Processing-In-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems

Takashi Takemoto, Masato Hayashi, Chihiro Yoshimura, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

Low-power embedded SRAM modules with expanded margins for writing

S. Shimada, K. Nii, N. Maeda, 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

A 1.3-Mbit Annealing System Composed of Fully-Synchronized 9-board x 9-chip x 16-kbit Annealing Processor Chips for Large-Scale Combinatorial Optimization Problems

Masanao Yamaoka, Chihiro Yoshimura, Kasho Yamamoto, 2021, 2021 IEEE Asian Solid-State Circuits Conference (A-SSCC).

4.6 A 144Kb Annealing System Composed of 9× 16Kb Annealing Processor Chips with Scalable Chip-to-Chip Connections for Large-Scale Combinatorial Optimization Problems

M. Yamaoka, C. Yoshimura, M. Hayashi, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

CMOS Annealing Machine: A Domain-Specific Architecture for Combinatorial Optimization Problem

Takashi Takemoto, Masato Hayashi, Chihiro Yoshimura, 2020, 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC).

Implementation and Evaluation of FPGA-based Annealing Processor for Ising Model by use of Resource Sharing

Masanao Yamaoka, Masato Hayashi, Chihiro Yoshimura, 2017, Int. J. Netw. Comput..

An Accelerator Chip for Ground-State Searches of the Ising Model with Asynchronous Random Pulse Distribution

Hiroyuki Mizuno, Masanao Yamaoka, Masato Hayashi, 2015, 2015 Third International Symposium on Computing and Networking (CANDAR).

Statistical measurement of random telegraph noise and its impact in scaled-down high-κ/metal-gate MOSFETs

M. Kobayashi, M. Yamaoka, E. Leobandung, 2012, 2012 International Electron Devices Meeting.

A 300-MHz 25-/spl mu/A/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor

S. Shimada, K. Kato, M. Yamaoka, 2004, IEEE Journal of Solid-State Circuits.

CMOS Annealing Machine: an In-memory Computing Accelerator to Process Combinatorial Optimization Problems

Takashi Takemoto, Masato Hayashi, Chihiro Yoshimura, 2019, 2019 IEEE Custom Integrated Circuits Conference (CICC).

Explore/exploit strategic movement of co-occurrence network based on a conscious/subconscious model

Yasuyuki Kudo, Takeshi Kato, Hiroyuki Mizuno, 2015, 2015 54th Annual Conference of the Society of Instrument and Control Engineers of Japan (SICE).

0.4-V logic-library-friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme

K. Ishibashi, M. Yamaoka, K. Osada, 2004, IEEE Journal of Solid-State Circuits.

SRAM Circuit With Expanded Operating Margin and Reduced Stand-By Leakage Current Using Thin-BOX FD-SOI Transistors

M. Yamaoka, R. Tsuchiya, T. Kawahara, 2006, IEEE Journal of Solid-State Circuits.

Efficient Ising Model Mapping to Solving Slot Placement Problem

Nozomu Togawa, Masao Yanagisawa, Daisuke Oku, 2019, 2019 IEEE International Conference on Consumer Electronics (ICCE).

An Ising model mapping to solve rectangle packing problem

Nozomu Togawa, Masao Yanagisawa, Daisuke Oku, 2018, 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).